Programming an FPGA using C Vs using openCL-C

Question

I came to know about Altera openCL devlopment Kit, for programming FPGA using OpenCL. I know what OpenCL is and how to write programs in this.
This is an extension to C, and it has threading possible. So you can launch thousands of threads, and each work in parallel if sufficient resources are provided.

MY question is from FPGA developer point of view how openCl development is different from C based FPGA development? (I have never programmed an FPGA in C) If you say OpenCL has parallelism, then I think when implemeneted in C, the final design after compilation and place and route will also have parallel units of hardware on the chip. So how is C and openCl different ?

Answer 1

First consider the difference between C and OpenCL. C is a language while OpenCL is a framework which includes all the resources required to compile to multiple targets and run these in parallel (queues/dispatch/sockets etc).

The Altera OpenCL 'kit' is similar in that it's not just a hardware compiler but also includes DDR controllers, PCI controllers, host drivers etc. This additional hardware that is built in the background and the host driver interface/dispatch etc is the major difference between coding in C and using C-to-HDL tools vs OpenCL for FPGAs.

With a C-to-HDL tool you still need to do the rest of the SOC and all the software drivers and applications to use an FPGA based algorithm accelerator card (for example). With OpenCL the same code can be compiled for multiple targets (cpu/gpu/fpga) without change (though this does add some constraints to what this code is).

And of course there are many good reasons to code the HDL yourself and build the SOC, Altera's OpenCL solution is a very interesting solution to General-Purpose-FPGA programming.

--edit--

For an example, see Altera's Mandelbrot reference design: http://www.altera.com/support/examples/opencl/mandelbrot.html From this you can see the primary source material is the cpp/h files and a board description file, the 'support' software and hardware to get your OpenCL kernel into hardware and talk to it is hidden from the OpenCL layer via the 'Altera OpenCL' SDK.

If you were to come up with a comparable solution using a C-to-HDL tool, you would start with the compiled kernel from the converter, then integrate this with DDR, PCIe and DMA hardware (the SOC) and then code the drivers for passing all this data around and integrate this driver with the OpenCL queue management system. Quite a bit of work.

Answer 2

The "kit" you are talking about is a tool that you can use to program and simply specify the hardware. It takes care of the hardware description language (HDL) for you probably as through a setting that you say what architecture you want and how many cores/threads. An FPGA doesn't come with cores or an instruction langue other than the ability to reset and set connections between logic blocks. If you don't specify the HDL either by presets like this tool or by manually designing one your code won't run. If I am missing your question please correct me.

I think what you are looking for is another vender supplied tool for FPGAs that lets you use the C language. In that subject I am not versed.

Using Google (using terms: C based FPGA tool).

Here is one such tool http://www.nallatech.com/Development-Tools/nal-a-c-based-development-environment-for-fpga-accelerators.html

It seems like these tools are all proprietary and are likely to only work on certain vendors FPGAs.

I hope that helps.

Answer 3

C-to-Gates tools help the FPGA developer use a subset of C as a hardware specification language. This C specification happens to be really easy to execute on a general purpose computer, so initial functional verification is fast and painless. (The intent is not to compile arbitrary C code into hardware.)

OpenCL for FPGA helps the software developer build hardware accelerators without having to learn about HDL or FPGA architectures.

Once you leave the world of FPGA vendor marketing and try to build real products, both of these technologies will require some combination of FPGA and software skill sets to produce good results.