Direct Coupling and No bias on JFET guitar preamp's

Question

Why some of JFET preamp's for guitars don't bias the gate to Vgs(off)/2 and just reference it to ground? (Setting Zi)

This also lead to just direct coupling the guitar output to the gate.

As far as I understand with N-JFET's one should apply a negative voltage up to Vgs(off) to control the current the channel. And that on the ohmic region near to Vgs=0 the transfer curve becomes more non-linear.

The direct coupling non-biased design would mean the preamp or voltage buffer would be working on the Vgs=0 non-linear zone and that on the positive semi-cycle of the input sine wave the gate will be forward biased and would not make the channel less resistive (since Ids is already max and the channel saturated) then the output would be quite different from the original.

One example of these designs:

Ruby: MPF102 input buffer for a LM386

Explanations like this one has a DC bias on the gate (that doesn't matters on the AC analysis though).

As far I have figured out if we put our reference on the Source, Rs is biasing both Source and Gate, making the Source more positive than the gate, and the Gate as negative as Vs.

But then on the Ruby circuit, taking the Source as reference, the Gate would be at -9V above the -8V needed to reach cut-off voltage on a MPF102 and -6V with a 2N5457. A positive semicycle above 1V should make a difference but a negative semicycle won't.

My approach is wrong? I know that DC and AC analysis should be done way different from this, but I don't understand the physics mechanics that are working here.

EDIT:

Setting aside that learn how things work is a good thing, I wanted to understand this to replace that MPF102 with an 2N2302 with smaller specs than the MPF102: Idss=5mA; Vto=-4V. (MPF102 and 2N5457 are not available here) I was worried if I would have to change values to achieve a proper polarization since my signal in a worst case scenario goes as high as 2Vpp and the MPF102 Vto is -8V. I understood that it was a voltage follower but failed to understand the inner workings so these questions came up.

Answer 1

Maybe this will help: -

For no particular JFET, the characteristic might be something like the above. Importantly, and ignoring when \$V_{DS}\$ is 5V or less, the gate bias voltage sets the operating current for the drain.

So, for JFETs with a simple gate bias connected to 0V, more drain current means more source current which means more source voltage which means a bigger negative bias on the gate relative to the source and this means "regulation" i.e. it finds its own level - there is negative feedback and very elegant it is too. This keeps it in the linear region.

For a guitar amplifier where the input signal is a few hundred millivolt p-p at maximum, the drain current is modulated by the gate ac voltage quite linearly.

If the supply is 10V (easy to see on the curve) and the gate voltage is 3V below the source, the drain/source current will be about 1.4mA and this is self-sustained (regulated) when the source resistance is about 2k2.

Picture stolen from here (a very good website for plenty of stuff).

Answer 2

There is bias on the gate and this bias is as expected negative:

As long as the bias is the voltage from the gate to the source:

$$ U_{gs} = U_g - U_s = 0 - positive < 0 $$

^{simulate this circuit – Schematic created using CircuitLab}

BTW, JFETs can work with 0 bias when the input signals are in mV range. Such small signals can't open the PN junction of the gate, so the gate current is still close to 0, but the slope of the JFET is maximal.

Answer 3

The JFET, like a vacuum tube triode, is normally "on". By placing a resistor in series with the source, the JFET "self-biases".

Since \$V_G = 0 \$ and \$V_S > 0 \$ for non-zero drain current, \$V_{GS} = V_G - V_S \$ is negative.

In words, think of it this way: the current through \$R_S\$ will be whatever it needs to be such the \$V_{GS}\$ is consistent with that current.

If \$I_D\$ were zero, \$V_{GS}\$ would be zero but this is inconsistent since, for zero bias, \$I_D = I_{DSS}\$.

If, \$I_D = I_{DSS}\$ then \$V_{GS}\$ would be negative but this is also inconsistent since, for negative bias, \$I_D < I_{DSS}\$.

Thus, we conclude that \$0 \lt I_D \lt I_{DSS} \$; the JFET has biased itself on.

In equations, we have, for the JFET:

\$I_D = I_S = \beta (V_{GS} - V_{TO})^2 \$

And, for this circuit:

\$V_{GS} = -I_S R_S = -I_D R_S\$

Thus:

\$I_D = \beta (-I_DR_S - V_{TO})^2 = \beta (I^2_DR^2_S + V^2_{TO} + 2I_DR_SV_{TO})\$

This is a quadratic equation in \$I_D \$ that can be solved for DC drain current.

Answer 4

The linked circuit shows an example of JFET "self-bias", which is a popular biasing method in general. It is not something particular to guitar preamps.

A N-JFET channel normally conducts, unless the gate is brought sufficiently lower compared to the source to achieve "pinch-off". In other words, it is a "depletion mode" device. So, the current flowing through the JFET generates a voltage on the source resistor, which lifts the voltage at the source terminal at the ground. The grounded gate is then somewhat negative with respect to the source, so the bias is somewhere between "full on" and "pinch off".

(A bias closer to pinch off results in less quiescent current through the channel, prolonging battery life, at the cost of less gain.)

You might be confusing JFETs and MOSFETs. The circuit configuration would not be appropriate for MOSFETS. That is, not for the more common enhancement mode MOSFETs, which are off unless there is a sufficient gate voltage above the source (or below, for P-channel). The self-bias circuit used for JFETS (which are depletion mode devices) is in fact appropriate for depletion-mode MOSFETS, which can be used in place of JFETs.