design data storage using a simple MUX instead of a complicated SR latch

Question

I was studying sequential circuits and I am at the very infant stages of the course. After studying the D flipflop I realized that the purpose was to let the data line change the output if clk=1 or keep the data same if clk=0. The circuit that is generally used is derived out of the SR latch which is a complex circuit using two feedbacks. Why cant I use a simple one feedback MUX circuit with the following boolean function?

Q(n+1)=Qn.C*+D.C

^{simulate this circuit – Schematic created using CircuitLab}

The circuit diagram at the gate level would be as shown above, where D is the data line and C is the Clock. Am I being dumb somewhere??

Answer 1

Assuming that your circuit works, and I'm not going to bother to find out, it isn't a fundamentally different circuit from an SR latch. You've removed the !Q output, so one of the feedback paths in the latch now looks like a feed-forward path. This seems intuitively true because you have shifted the OR gate to the right, so the path from the bottom AND gate to the OR gate doesn't look like a feedback path anymore.

In any event, the important characteristic is not the number of feedback paths but the number of gates. You replaced a nice 2-gate latch with four gates, so most people would say you've taken a step backwards. Worse, the natural gate style in CMOS is NOR and NAND rather than OR and AND so your solution might actually require additional inverters for a practical implementation.

Answer 2

Your circuit is not balanced. Path delay for clock signal to reach AND1 and AND2 is different. Therefore clock signal will reach the inputs of two AND gates at different time. Hence if circuit is driven by high speed clock there may a case where clock drives both AND gates at the same time.