3-bit multipliers - how do they work?

Question

I need to understand how 3-bit multipliers work and then I must design one. I've read through Wikipedia's binary multiplier but I just can't wrap my head around it. I don't understand where to start. Could you please explain to me what happens when two 3-bit numbers are run through a 3-bit multiplier? Maybe then I can reconstruct each step in a circuit on paper. Alternatively, could you outline the relevant sub-concepts I need to grasp?

In general, I'm thankful for any help in understanding 3-bit multipliers.

EDIT: Thank you to everyone who contributed to this Question. You all helped me understand the relevant concepts, and so I wish I could accept all answers as solutions.

Answer 1

If you're a EE/CPE student and you're just starting to learn logic, maybe you haven't learned this yet but you will.

Arithmetic and logic functions are essentially realized in circuit form by starting with a truth table and filling in the values that implement the function you want. For 2x2 bit multiplication, this is the truth table:

From the program Logic Friday

Go through each row, and you'll see how it implements it. It is in the form A0,A1 * B0,B1 = F0,F1,F2,F3

Sorry, it's backwards as typically the LSB is A0 or B0, I numbered it wrong. Anyways, take for instance the last row. It says 11 * 11 = 1001. In decimal, that's just 3 * 3 = 9

After the truth table is complete, you could fill this into a karnaugh map, and derive the equations for each output of the circuit. In this case, I let this handy program do it for me.

The output came to this.

At this point, you can see that I have an equation for F0 through F3 based on the inputs. Now I just need to throw in the logic gates to match those equations. And voila, you have a circuit that performs binary multiplication.

This is the simplistic side of it. Real processors and the ALUs inside of them don't exactly do it this way. For instance on a 64-bit computer, the amount of combinational logic necessary to perform 64x64 bit multiplication would be insane. Instead, as the wikipedia article you read states, they multiply one of the 64-bit operands by each individual bit of the 2nd operand, each time shifting the result. Finally, they add all of the partial sums together. That is the absolute most simplistic method of performing the multiplication sequentially. Some processors though have even faster multiply implementations that make use of wallace trees

Also, if you'd like a little more insight on the sequential type multiplier, here you go. This may be a little more difficult so don't worry about understanding how each of the components works underneath, because you will learn it soon. I leared shift registers, ALUs, and all that by the end of my first digital logic course.

This image comes from http://faculty.kfupm.edu.sa/COE/mimam/files/COE200experiment13.pdf

This is a simplified 4x4 bit version, and it goes sort of like this:

1) The 4-bit multiplier is loaded and stored in the P shift register, specifically Pl. Also, the 4-bit multiplicand is stored in the B-register. Ph is all 0's

2) On each clock cycle, the P register is shifted to the right, and the rightmost bit, P0, is sign-extended (not shown, to make it 4 bits), and ANDed with the multiplicand in the B-register. If you go back to the binary multiplier page on wikipedia, under multiplication basics, the 2nd grey area, you can see this happening with each staggered row, it is an AND operation that essentially does the multiplication since each time it is either multiplicand x 0, or multiplicand x 1.

Since the ALU is performing the add operation, the result of the 1 bit multiplication is added to the previous partial sum, in this case 0 since this is the first step, and stored in Ph.

3) On the next cycle, the P register is again shifted, and so you can see how the Ph output gets shifted and added again to the result of the 1-bit multiplication.

4) At the end, you have an 8-bit result stored in the p register.

Answer 2

This may not be what you are looking for as far as getting insight into a regular multiplier circuit, but you can implement this easily with just a ROM. All you need is 64 memory loctions, each 6 bits wide. You load the ROM with answers to each of the possible 64 input cases, and the rest is a lookup.

This may sound dismissive, but actually small multiplies and other more complicated functions are often implemented with a lookup table. This would be the normal way to do it inside a FPGA, for example. As the words get wider, the lookup table method becomes impracticle, but for just 3 x 3 it is probably the most appropriate way to implement a multiply in most real cases.

Answer 3

Write the multiplication down and you'll know what to do. For example A₂A₁A₀×B₂B₁B₀

            A₂   A₁   A₀
         ×  B₂   B₁   B₀
 -----------------------
          B₀A₂ B₀A₁ B₀A₀
+    B₁A₂ B₁A₁ B₁A₀
B₂A₂ B₂A₁ B₂A₀

As you see, just multiply each bit (which is accomplished by an AND) then add them together using full adders. Here is an implementation

Here is a different way to draw the implementation

Most other online examples are 4-bit multipliers but you can modify it easily to make a 3-bit one

• Hardware Multipliers

  

• Combinational Multiplier