All I know is that although Cortex-M3/4 micros are Harvard architecture, they can run code from RAM, at least some implementations can (like STM32F4). Can Tiva C series microcontrollers execute from RAM?

  • 2
    \$\begingroup\$ Have you read the datasheet? \$\endgroup\$
    – markt
    Feb 18, 2014 at 9:00

2 Answers 2


Tiva™ TM4C123BE6PZ Microcontroller Data Sheet

It's not immediately obvious from the datasheet, but look on page 87-88:enter image description here

It has two buses but only one address space; so you can execute programs from several regions, but you are advised that you only get the benefit of being able to do an instruction fetch and data fetch at the same time if they are from different regions.

  • \$\begingroup\$ Of course this means that executing code from SRAM will be slower? Flash, from what I understood, has wait states when operating over 40 MHz that are mitigated by using prefetch buffer. \$\endgroup\$
    – Michał B.
    Feb 20, 2014 at 3:02
  • 2
    \$\begingroup\$ I would assume that internal SRAM was single cycle unless it says otherwise. \$\endgroup\$
    – pjc50
    Feb 20, 2014 at 8:09

On-chip memory

32 KB single-cycle SRAM located at 0x2000.0000(for code storage)

■ 256 KB of single-cycle on-chip Flash memory(page 528)

■ 2KB EEPROM(for non-volatile data storage)

The program is stored in flash and variables in SRAM

@pjc50 is spot-on with the image and description.

The Cortex-M4F prefetches instructions ahead of execution and speculatively prefetches from branch target addresses

[1] Page 96 of TIVA C Datasheet


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