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We are supposed to find \$R\$ such that \$I_S=0\$ and then find the maximum \$V_{SRC}\$ for operation in the linear region. I tried to use KCL at the nodes but it didn't work out eventually since I got a value of R that is negative. And for the second part of the question how does one determine the maximum possible value in the linear range: I am not sure how to go about this. I would appreciate any help.


Step by step:

The current, from left to right, through \$R\$ is

$$I_R = \frac{V_{SRC} - V_{O2}}{R} $$

The current, from left to right, through the left-most 10k resistor is

$$I_{10k} = \frac{V_{SRC}}{10k\Omega} $$

KCL at the input node yields

$$I_S = I_R + I_{10k}$$

Using the well-known inverting op-amp gain formula, the two op-amp cascade has a gain of

$$\frac{V_{O2}}{V_{SRC}} = (-\frac{40k}{10k}) \cdot (-\frac{20k}{10k}) = 8 $$

Now, set \$I_S = 0\$ and solve.

A rewarding exercise is to solve for the input resistance seen by the input voltage source:

$$R_{IN} = \frac{V_{SRC}}{I_S} = \frac{V_{SRC}}{I_R + I_{10k}} = \frac{1}{\frac{1}{10k\Omega} - \frac{7}{R}}$$

Note that the input resistance is positive for \$R > 70k\Omega\$, is negative for \$R < 70k\Omega\$ (the circuit supplies power to the voltage source), and is 'infinite' (open circuit) for \$R = 70k\Omega\$

  • \$\begingroup\$ I have to admit the cascading formula that you provided does make the solution quite easy. Thanks. I will also try out Andyaka suggested method, of setting 1V. For the second, how does the second part work? The answer should be +/- 1.5V, but I don't know how one gets that answer. \$\endgroup\$ – user29568 Feb 19 '14 at 13:38
  • \$\begingroup\$ @user29568, note that the schematic indicates +/- 12V power supplies for the op-amps so we have $$-12V \lt V_{O1}, V_{O2} \lt 12V$$ Thinking about that limitation and the overall gain, what must be the range of \$V_{SRC}\$? \$\endgroup\$ – Alfred Centauri Feb 19 '14 at 13:41
  • \$\begingroup\$ I am getting +3, when I am setting the output of the first op-amp as 12 V. \$\endgroup\$ – user29568 Feb 19 '14 at 13:50
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    \$\begingroup\$ @OlinLathrop, it's not hard to check and verify that the answer was given before I posted my answer. As far as I'm concerned, if other posters have provided the answer, there is no reason not to provide a detailed analysis that provides a proper example of how the problem is to be approached. So, not only am I not ashamed, I'm certain my answer is appropriate. \$\endgroup\$ – Alfred Centauri Feb 19 '14 at 17:08
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    \$\begingroup\$ @user29568, the 2nd op-amp will saturate first, when the 1st op-amp output is +/- 6V or greater which is when the input is -/+ 1.5V. I'm not sure why you would want to reason otherwise. As soon as the 2nd op-amp saturates, there is no longer a virtual ground at the inverting input of the 2nd op-amp so your calculation of the resistor current isn't valid. \$\endgroup\$ – Alfred Centauri Feb 19 '14 at 20:28

Start by forgetting about Vsrc and R, and just analyze the the two-opamp circuit by itself. You should be able to see what each stage does from inspection, which then easily gives you what both stages together do. Not even a calculator is needed here.

Now consider the input impedance of this circuit. What is it? It should also be obvious from inspection. This gives you a certain current the two-opamp circuit will draw from its input for any particular voltage. Now consider what voltage is on the right side or R for any particular input voltage. This current thru R must be the same as that drawn by the inut for Vsrc to have no current thru it.

Now stop and think about what this circuit is really doing. Start out with R infinite and consider what happens as R is lowered. At inifinite R, this is just the basic two-opamp circuit that should be obvious. Can you see that as R decreases, it supplies ever more current to the input? The effect is that it increases the apparent input impedance of the overall circuit. Eventually R gets to the point where all the input bias current is exactly offset, which is what this question is asking about. At that point (ideally) you have a circuit with infinite input impedance. If you keep going and make R smaller, you get something called hysterisis if Vsrc has any positive resistance.


If you regard V\$_{SRC}\$ as an input, the output of the 2nd op-amp will be 8 x V\$_{SRC}\$ and ideally the resistor R and the 10k resistor should form a potential divider that would recreate V\$_{SRC}\$ as if V\$_{SRC}\$ wasn't there.

This would mean that when V\$_{SRC}\$ becomes connected, it would see an exact replica of itself and no current would flow i.e. I\$_S\$ would be zero.

For the 2nd part, if the op-amps were rail-to-rail perfect devices, the maximum magnitude of voltage seen would be on the output of the 2nd op-amp - this cannot be greater than 12V - knowing this means you can calculate what V\$_{SRC}\$ limits are.

  • \$\begingroup\$ Then aren't we supposed to know what \$V_{SRC}\$ is to find R \$\endgroup\$ – user29568 Feb 19 '14 at 13:13
  • \$\begingroup\$ @user29568 Imagine it was 1V - the o/p of the 2nd op-amp will be 8V. Now imagine the 8V was fixed like a battery - if R became 70k, the voltage at the input (when the voltage source is removed) would be 1V - exactly the right voltage so as not to take current from Vsrc when it reconnects. Try it your self at a different voltage and see what R becomes - you won't be disappointed!! At 70k, the input impedance becomes infinite. \$\endgroup\$ – Andy aka Feb 19 '14 at 13:22

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