The simple RC-model for mos transistors in digital circuits, brought in CMOS VLSI Design book by West-Harris is like this:
But in other sample of book a 3-Input nand gate modeled like below:
When I modeled the circuit using basic model, I noticed that there is a missing Capacitor at highlighted node. There should be two parallel capacitors: one among Source-Body of B, call it Csb(B) and other one among Drain-Body of A, call it Cdb(A).
Since both of them assumed to be grounded they should lead to a 6C capacitor at highlighted node.
What I want to know is that depicted model got typo errors or I missed something in my considerations?