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I have a circuit board with an oscillator and I'm curious about why there is a capacitor hooked up to the output. The oscillator is a SWO series HCMOS Square Wave output crystal oscillator. The schematic of the oscillator connections is as follows.

               +3.3V
                |
   ---------    |  C=0.01uF
NC-| 1   4 |---------||-----GND
   |       |
GND| 2   3 |---------->Direct to FPGA input pin
   ---------    |
                |
                = C=15pF
                |
               GND

The data sheet (select H22/H32/H53/SWO) does not reveal much, but there is a "Load" section that says the max load is 15pF. Specifically, it says:

Load | 15 pF ; ( 30 pF and 50 pF load are also available for +3.3V and +5.0V VDD)

In such a circuit, is the load the capacitor or the FPGA input pin? If the load is the capacitor, why is the load needed for the oscillator? What is its purpose?

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2 Answers 2

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They have a technote paper on this subject, "Effect of Load Capacitance on the Crystal":

http://www.mecxtal.com/pdf/te_notes/tn-021.pdf

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The 15 pF load capacitance mentioned in the data sheet is the total load that should be placed on the output - printed circuit track capacitance, input capacitance of the devices it drives, etc.

That capacitor should be removed, it will adversely affect the signal.

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  • \$\begingroup\$ Interesting, the board is from Lattice Semiconductor. I could easily remove the cap, but what type of adverse affect will it have on the clock signal? Will it cause delays or deform the clock waveform? \$\endgroup\$
    – Dr. Watson
    Commented Feb 12, 2011 at 16:49
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    \$\begingroup\$ It would increase the rise and fall times. Perhaps that is the reason for including it. \$\endgroup\$ Commented Feb 12, 2011 at 16:54

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