FPGA output pin high capacity load

Question

I am writing an interface for a HITACHI SX19V001-ZZA that is a color LCD display. Please have a look at the datasheet (pages 13-14) to understand the references I am going to make.

My interface sadly does not work but I checked with a scope and all the timing requirements are met, although I am not very sure about the relationship between CL1 and CL2: the first is the "first line marker" while the second tells the display when to sample the 8 bit parallel input. What I do not understand is what the "first line condition" is, I mean, should CL1 be high while CL2 goes low (page 13)? Because that's not what I understand looking at the timing requirements.

That said, my real problem is another. CL1 pin has an input capacitance that is over 300pF while the other pins are around 50pF. I measured this with a simple tester so these values are not particularly reliable, anyway when I connect the display to the FPGA the waveform of CL1 is everything but a rectangule, being a little bit under 100ns of rise and fall time, that is double the maximum allowed. My quick fix idea is to assign CL1 to two outputs of the fpga and connect both of them to the display CL1 input, just to see if my problem is its rise and fall time, or somewhwere else.

The generic question then is: is it safe to shortcircuit two FPGA output pins given that they are driven by the exact same wire in the verilog/vhdl/whatever description?

Some random infos: currently my CL2 frequency is 3.125MHz to achieve a frame rate around 27 FPS, CL1 is shaped exactly as per page 13, not meeting the rise and fall time as stated, it starts to rise when CL2 rises and starts to fall at the next CL2 positive edge. The frame sync (FLM) is pulled high when CL1 rises, and it is pulled low at the next CL1 positive edge. Of course CL1 and FLM are pulsed at the correct frequency, the first one every 240 CL2 and the second one every 480 CL1. The FPGA is an altera cyclone II (development board DE2)

Answer 1

It is an absolutely industry-standard practice to connect several outputs of an FPGA or MCU to combine the power of the individual output drivers as long as you make sure that all of them are controlled by the same signal.

Answer 2

As Lazlo mentioned, you should check the current strength and slew rate settings first. That would be a preferred solution to shorting pins together.

The easiest way to verify or change I/O settings is from the Pin Planner. You can start launch the Pin Planner from within Quartus under the Assignments menu.

If you can't achieve the drive strength you need then certainly shorting pins is an option. I wouldn't think twice about using this technique for a home project. If I were using this technique on a production design then I would want to talk to the FPGA vendor to get clarification. Some things you want to think about are, are the shorted pins in the same or different I/O banks, and, does shorting the pins impact decoupling requirements.