# Organization of large memory using memory blocks

I found the following question in a test. I am not looking for an answer to the question per se, but I am having difficulty understanding the part in bold, as explained below.

A main memory unit with a capacity of 4 megabytes is built using 1M×1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is?

As far as I know, an m x n memory chip has m rows of n cells each. Hence, the given chip should have 1M rows of 1 cell each. How come the bigger memory unit built out of it has 1k cells in each row?

What is the mistake I am making here? Is my understanding of the memory chip specification incorrect, or is there a way of reconfiguring memory chips to have more columns per row that I do not understand? Can someone please explain this to me?

## 2 Answers

From the outside, each memory chip is organized as 1M words of 1 bit each, which means that it takes 20 address bits to specify a word.

Internally, the memory is physically organized as a square matrix of 1024 rows and 1024 columns, with one bit in each position in the matrix.

There are at least two reasons that the physical organization is important to the question:

1. The memory chip only has 10 address pins. The full 20-bit address is fed into the chip in two stages, the 10-bit row address first, and then the 10-bit column address.

2. When a refresh operation occurs, an entire row is refreshed all at once.

• I see, so the 1Mx1 refers to how the external world sees it, not how the chip is internally organized. That was the source of my confusion, I guess. Commented Feb 23, 2014 at 4:44

How the interface is organized has nothing to do with how the memory is logically organized, nor how it is physically organized. Your basic assumption that the row size is equal to the word size is incorrect.

• I don't get what you mean by interface, logical and physical. In the Computer Organization textbook I am reading, it says that a m x n chip has m rows of n cells each. I know it can be addressed in different ways by organizing the address bits into rows and columns, but that's not what I am asking for. I want to understand how the chip is physically organized. The refresh is done on a per row basis, so a chip having 1M rows of 1 cell each, versus 1k rows of 1k cells each, or any other arrangement does make a difference. Commented Feb 23, 2014 at 4:37
• In particular, how is it possible that a 1Mx1 chip gets reconfigured into 1k rows of 1k cells? Or does 1Mx1 not mean the no. of physical rows and columns? If so, what does it mean? What is the difference between 1Mx1 chip and a 512kx2 chip? Can the same chip be called by both the names? Commented Feb 23, 2014 at 4:38
• The chip is never "reconfigured". It has rows that are of one size, and the interface accesses it a different way. There is no requirement to transfer an entire row of data at once into or out of the chip. Commented Feb 23, 2014 at 4:43