We are using the LTC5800-IPM microcontroller in a project. The way our design is now, the IC's GPIO pins will sometimes be driven high (to 3.3V) or low when it is powered-off. Will this weaken the chip? The absolute maximum ratings state the voltage on any digital I/O pin is -0.3V to VSupply+0.3V. If the answer is no, could the IC be weakened during power up?

The LTC5800-IPM does not have the most detailed datasheet. If it is not clear for that device in particular, I'd be interested to know for CMOS microcontroller GPIOs in general.

  • \$\begingroup\$ Define "weakened." \$\endgroup\$ – JYelton Feb 24 '14 at 20:41
  • \$\begingroup\$ What is VSupply for the controller while "powered-off"? \$\endgroup\$ – jippie Feb 24 '14 at 20:45
  • \$\begingroup\$ It's on the other side of a load switch, so Vdd is just disconnected. \$\endgroup\$ – BenYL Feb 25 '14 at 2:32

Yes, it's possible to damage the chip by driving it from a low impedance source when Vdd is 0.

As you read from the datasheet, the absolute maximum input voltage is Vsupply -0.3. So if Vsupply is 0, you should not apply more than +/- 300mV to any input.

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As well as possible damage to the particular I/O pin's protection network, if you apply power when there is an input being driven from a low impedance source, it can cause latchup, which will either short the power supply to a low voltage or destroy the chip (maybe both).

To isolate the two devices, you could use a voltage translator such as the 74AVC1T45, which goes high impedance if either Vdd is 0.

The protection network is something like a small diode between the input and Vsupply (and something similar to GND) and usually some series resistance, either of which can be damaged if you drive too much current through the input. If you drive the input to (say) 3.3V, current will flow out of the Vsupply pin and into whatever else is connected externally. At a minimum this is a big load on whatever is driving the chip even if it does not immediately cause damage.

Latchup (as described in detail in the link above) is an effect caused by the parasitic SCR structure inherent in most CMOS ICs. If a low-power chip is getting very hot to the touch, it's probably latchup.

  • \$\begingroup\$ How about if we put series resistors on any lines driving the powered-off chip? \$\endgroup\$ – BenYL Feb 25 '14 at 14:49
  • \$\begingroup\$ @BenYL Officially, for this particular chip, that is not allowed (see above). Some chips have a current limit spec that covers this situation (you're allowed to exceed +/-0.3V iff you limit the current to the specified value. In practice, it's frequently done and it works (with some caveats) provided the current is limited sufficiently. \$\endgroup\$ – Spehro Pefhany Feb 25 '14 at 14:52

Unless the datasheet and associated documentation specify otherwise, do not apply a non-ground voltage to an unpowered device. The device may become powered through the input protection diodes on the pin and could behave erratically.

If there is no way to modify the schematic such that unpowered devices do not have voltage applied to their inputs then use tri-state buffers such as the 74HC125 or 74HC244 to hi-Z the inputs when power is not applied to the device.

  • \$\begingroup\$ The interesting thing is we already have buffer chips in the design because the LTC5800 is connected to another similar device. Either chip may be powered while the other is not. I need to somehow protect both chips. \$\endgroup\$ – BenYL Feb 24 '14 at 21:14
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    \$\begingroup\$ Then use something like the TXB0104 that hi-Zs if either side is unpowered. \$\endgroup\$ – Ignacio Vazquez-Abrams Feb 24 '14 at 21:21
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    \$\begingroup\$ Be careful with parts like the TXB0104- the LTC5800 may not have enough drive capability to reliably control the direction. I`ve had to fix designs with that problem. \$\endgroup\$ – Spehro Pefhany Feb 24 '14 at 22:51

I'm going to use CMOS IC CD4066 for similar situation. It has wide supply and input/output voltage range and four bi-directional switches. The voltage between two systems should be equal, thus not violating the maximum permissible voltage for the GPIO inputs compared to Vdd. The frequency of the communication protocol must be taken into account.

Georgi Motev


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