Xilinx developed a way to combine multiple dies in a single package by using a silicon interposer (I don't know whether they're actually are the first ones to do this). This way, they achieve huge bandwidths between the individual dies, much more than would be possible if the signals had to go through IO pins (for more details, see here or refer to the whitepaper).
Now why doesn't Intel, for example, use a similar technique to combine the CPU and the RAM in one package? This would allow for a much higher memory bandwidth, among other benefits (slightly lower latency, lower power dissipation, fewer package IO pins, fewer signal routes on the mainboard).
Sure, there are some drawbacks (the DRAM chips would have to be stacked, the amount of RAM is fixed, an additional interposer die is needed (though this can be manufactured in an older, cheaper process node)), but considering that the memory bandwidth bottleneck is an increasing problem for a growing number of cores, this should be worth it. What am I missing?