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Xilinx developed a way to combine multiple dies in a single package by using a silicon interposer (I don't know whether they're actually are the first ones to do this). This way, they achieve huge bandwidths between the individual dies, much more than would be possible if the signals had to go through IO pins (for more details, see here or refer to the whitepaper).

Now why doesn't Intel, for example, use a similar technique to combine the CPU and the RAM in one package? This would allow for a much higher memory bandwidth, among other benefits (slightly lower latency, lower power dissipation, fewer package IO pins, fewer signal routes on the mainboard).

Sure, there are some drawbacks (the DRAM chips would have to be stacked, the amount of RAM is fixed, an additional interposer die is needed (though this can be manufactured in an older, cheaper process node)), but considering that the memory bandwidth bottleneck is an increasing problem for a growing number of cores, this should be worth it. What am I missing?

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    \$\begingroup\$ Don't Intel call it on-chip cache? \$\endgroup\$ Feb 25, 2014 at 14:43
  • \$\begingroup\$ Two chips dice sitting by side will have twice the available surface area of dice that are stacked. Stacking dice may save a little energy, but in many computers getting energy out of the CPU is a bigger problem than getting it in. \$\endgroup\$
    – supercat
    Feb 25, 2014 at 16:21
  • \$\begingroup\$ @supercat I'm not sure I understand your comment. IO activity will always generate waste heat in the reading and the writing chips. \$\endgroup\$ Feb 25, 2014 at 19:19
  • \$\begingroup\$ @AdrianWillenbücher: I/O will generate some waste heat, but processors generate a lot of other waste heat. Stacking dice will eliminate some of the heat caused by I/O, but may make it harder to get rid of the heat which would still be generated by other sources. Stacking chips may be useful despite the thermal issues, but the thermal issues are severe enough to limit the benefits of stacking. \$\endgroup\$
    – supercat
    Feb 25, 2014 at 20:04
  • \$\begingroup\$ @supercat Sure, that's why I suggested putting the CPU die and the DRAM dies side-by-side; the DRAM dies produce little enough heat that they can be stacked. \$\endgroup\$ Feb 26, 2014 at 5:39

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why doesn't Intel, for example, use a similar technique to combine the CPU and the RAM in one package?

They (will) do?

Intel's Rajeeb Hazra, a VP and general manager of its data centre group, said Intel would customise high-end Xeon processors and Xeon Phi co-processors by closely integrating memory, both by adding memory dies to a processor package and, at a later date, integrating layers of memory dies into the processor

enter image description here

The amount of in-package memory would be limited by real-estate limits, the physical space inside the package, and we shouldn't expect such Near Memory to replace or substitute for Far Memory.

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  • \$\begingroup\$ Interesting. Have they released any more details about this? (I couldn't find any) \$\endgroup\$ Feb 25, 2014 at 19:12

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