I'm working on a DDR3 layout at 533Mhz clock speed in a balanced T configuration. I am currently unable to route the address/ctrl lines with an equal amount of vias (+1 on a limited number of lines). All the lines have been routed to the same length within 20 mil.

I have calculated my via delay as 68 picoseconds which corresponds to an entire cm difference in the effective length of those lines, board propagation speeds have been calculated as 54ps and 69ps per cm external/internal respectively. At 533Mhz the signal propagates 13.6 cm to 17 cm (depending on internal/external layers) in half a cycle which translates to about a 6-7% skew for those lines.

Can I rely on DQS and write leveling calibration to absorb this difference in effective lengths or should I shave a cm off the lines with the additional vias?


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The big advantage of DDR3 over DDR2 is that it allows the address/ctrl bus to use fly-by topology instead of balanced T. Fly-by is the recommended and easiest topology for DDR3. Balanced T is still possible for DDR3, but it is discouraged.

Write leveling and read leveling should indeed be able to handle your mismatched delays. That is not the problem here. You problem will instead be mismatched reflections, which will affect your signal integrity.

I recommend you solve the problem by switching to fly-by topology. It is explained a bit here: https://www.youtube.com/watch?v=7sxBBvF12JY


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