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I'm using some QFN devices in a PCB I'm designing using the Eagle PCB software. The QFN packages have a centre pad that is grounded and intended to help with thermal dissipation.

When creating the package, if I have the centre pad as an actual pad then I get DRC errors when I come to place vias on the pad to connect it through to the ground plane on the opposite side of the board.

Another possibility would be to leave the centre pad off the package and draw it in on the board, but this is a pretty unsatisfactory solution.

What's the best way of dealing with this problem?

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  • \$\begingroup\$ See this similar question on QFN packages. You could follow the same procedure without messing with the stop mask. \$\endgroup\$ – W5VO Feb 14 '11 at 20:10
  • \$\begingroup\$ @W5VO thanks, that's an interesting question. Unfortunately part of the advice is "ignore the DRC errors". \$\endgroup\$ – ralight Feb 15 '11 at 12:28
  • \$\begingroup\$ The best way to handle the problem is very carefully approve the DRC "error". It is a limitation of the software. \$\endgroup\$ – W5VO Feb 15 '11 at 13:24
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Ok, I've found a solution to this problem.

The answer is to place the centre pad in the package with "stop" and "cream" turned off, then manually draw in rectangles for the "stop" and "cream" layers over the pad as they would've appeared anyway.

The physical end result is the same, but placing vias on the pad doesn't produce DRC errors.

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When you create the package/schematic for the part assign the center pad to an extra pin on the schematic symbol and tie it to the proper signal (usually GND or occasionally VCC).

If you don't want to confuse the schematic, in most design tools you can hide a pin and internally connect it to another pin. So you'd just hide the pin for the center pad and tell it that its grouped with a GND pin or whatever signal it should be coupled to.

Doing that should allow you to pass DRC checks. Some design tools would treat multiple VIAs as a signal loop and remove them, you may have to set flag for the particular signal to avoid that check. I've had to do this with Altium in the past but i don't think Eagle does automatic loop removal so you can probably skip this.

If the center pad is for thermal management, you need to make sure your using enough vias to conduct the heat. In that situation i usually include the required number/size of vias in the actual package design and only nudge them around in the final PCB layout if I really need to. I don't recall off the top of my head if eagle allows exploding package footprints for editing on the PCB or not.

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  • \$\begingroup\$ From what I know: The syntax in Eagle to avoid confusing a pin is to name it, for example, GND@1 and GND@2, and then (I forget how) these pins are linked. Eagle does not use automatic loop removal. Eagle does not allow exploding package footprints, though vias are allowed in the package design. \$\endgroup\$ – Kevin Vermeer Feb 14 '11 at 20:10
  • \$\begingroup\$ Thanks but I'm afraid your reply doesn't really address my problem. I've already got the bits you suggest down pat :) \$\endgroup\$ – ralight Feb 15 '11 at 12:30
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Just put the vias in the pad and live with the DRC errors. With the Pulsonix software I use I can put vias in pads without DRC errors provided they are assigned to the same net. Perhaps you can do the same with Eagle. I can also create pads of any shape with one or more vias in them.

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  • \$\begingroup\$ Thanks for the suggestion, but the DRC errors are exactly what I'm trying to remove. \$\endgroup\$ – ralight Feb 15 '11 at 12:27
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    \$\begingroup\$ You don't seem to have any other option, it looks like an Eagle limitation. \$\endgroup\$ – Leon Heller Feb 15 '11 at 13:58

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