# Stable states of RS latch

I am a novice when it comes to electrical engineering and I have a very basic question concerning the operation of RS latches:

I am currently working my way through Roth/Kinney's Fundamentals of Logic Design and I have some problems understanding the part describing the operation of RS latches. The book gives this table for the states of RS latches where Q^+ = R'S + R'Q and P = S'Q' and the stable states of the latch are circled: Now, how comes that for SR = 01, Q = 1 and SR = 10, Q = 0 the latch does not end up in a stable states. I thought that that as long as SR != 11 the latch always ends up in a stable state.

Also, for SR = 11, Q = 0, how can the latch end up in a stable state. I thought that setting SR to 11 is forbidden and the latch state is undefined for this input combination.

Can anybody clarify that for me?

• 'stable' means 'is going to stay in the same state'. For Q=1, SR = 01 (i.e. Q=1, S=0, R=1) (R)eset is high. Next state is going to be 0. So the state will change. Q=0, SR=01 is stable because R doesn't do anything if Q is already 0. We can also see from SR=11, Q=0 that R overrides S, i.e. if you try to both set and reset this latch you get 0 as your next state and that it stays there rather than oscillates – Will Apr 2 '14 at 15:13

## 2 Answers

If SR is 11 then the outputs of the cross-coupled NOR gates is 00 (defined).

(from the book) Assume typos in this book..

The particular latch circuit you describe is not the typical SR latch. Notice that there is no feedback from Q` to Q. I think this latch gives precedence to R over S, so that a transition from SR=11 to SR=00 will leave the latch in the reset state.

• I'll go one further, and say that the circuit described IS NOT an SR latch. – Scott Seidman Apr 1 '14 at 15:30