Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
I have a question in my text book that I do not quite understand. I was wondering if someone could please explain what the question means? Such as, what is a deskewed flip flop. How would one find the max frequency of the clock from the diagram?
Below is the question (8.83) with the corresponding diagram at the bottom:
I used almost this exact same circuit many years ago when I did hardware design and I would need a better memory and time to remember the details. It's not a "deskewed flip-flop" but a "deskewing flip-flop". The idea is to make sure the asyncronous input to the system occurs in line with the system clock and doesn't change erratically. The flipflops help latch the data in and hold it stable till the system gets a chance to handle it.
I wish I had the time to think this through but it's been almost 20 years since I've done this and I think I might be getting old.
To find clock frequency we need to find the minimum required time for data to pass from FF2 to FF4. Here FF2 is the launching flop with clock CLKN. CLKN is the output of clock divider FF3. So CLKN = CLK/2. Since CLKN comes from a flipflop output, it will lag the the CLK signal by the propagation delay of that flipflop. This delay is 10.5ns.
FF4 is the capturing flop with clock CLK. So we have datapath with different launching & capturing clocks. Here is a simplified diagram:
and here is the timing diagram for this path:
tpd_FF3 is lag time between CLK an CLKN. The curved arrow shows the timing window for this path. In this path we will have additional propagation delay for FF2 marked as tpd_FF2. And of course the setup time for FF4, tsetup. Now to operate this circuit correctly, we must have,
$$ T_{CLK}- t_{pd\_FF3} - t_{pd\_FF2} > t_{setup} $$ $$ T_{CLK} > t_{pd\_FF3} + t_{pd\_FF2} + t_{setup} $$
so, the Minimum value of T = 10.5 + 10.5 + 4.5 ns = 25.5ns and maximum frequency for CLK is 1/25.5ns = 39.2Mhz
If there is no deskewing flop FF4, CLKN signal will always lag with CLK signal. So you'll have a skew between launching & capturing clocks in the synchronous system. If you have other combinational elements in the datapath before going to the synchronous system, the path will have less time to be stable because of this skew. After adding the FF4 that additional skew in the clock path will be removed, because now both launching & capturing clocks are same.
