# Johnson Counter VHDL

I have a problem given to me that states:

Design a 4-bit Johnson counter and decoding for all eight states using just four flip-flops and eight gates. Your counter needs not be self-correcting.

I wrote my VHDL code for the 4-bit Johnson counter, but I am confused as to what it means by decoding for all eight states, using eight gates? Do I need to have combinational logic to implement this? If so, how would I implement that in vhdl?

Here is my code:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity eightRC is

port(
CLK : in    std_logic;
EN: in  std_logic;
RST : in    std_logic;
Q: out  std_logic_vector(7 downto 0)
);

end eightRC;

architecture behavior of eightRC is
signal qs: std_logic_vector(7 downto 0);
begin
process(CLK, RST, EN)
begin
if(RST = '1') then
QS <= "11111110";       --initial state for QS
elsif (CLK'EVENT AND CLK = '1' and EN = '1') then     --enable starts the shifting
QS(0) <= QS(7);            --shift '0' to the left each clock edge, Q(0) gets Q(0) bit value
QS(7 downto 1) <= QS(6 downto 0);
end if;
Q <= QS;
end process;
end behavior;


You have not written the code for a 4-bit johnson counter. You have written code for an 8-bit johnson counter.

You are asked to create an 8-state johnson counter using 4 flip-flips, so clearly you cannot just use an 8-bit variable in your VHDL code and loop it through like you have done, as that is using 8-flip flops.

It looks like you're familiar with the basic type of johnson counter that looks like this:

As you can probably deduce, the input gets the inverted output of the last flip-flop. Because of that, starting from a RESET condition of all 0's, a pulse train of 4 0's or 4 1's passes through the johnson counter, and the output looks like this:

Now consider that you might want 8 output bits, and 8 states where in each case only 1 bit is high, like a typical counter would produce, while using only these 4 flip-flops. In order to create that output, you need to add some logic gates. Since you must create those output bits off of the output from the basic johnson counter, you can see that you need some logic that combines some of the output states to create the new ones.

Now consider this picture. In order to create the states required, your gates need to be connected to output combinations that are unique

Where the red line is, a unique state exists with ~Qa * ~Qd, as you can see the cycle before Qd was high, and on the next cycle Qa will become high, therefore this state exists only once.

For the green line, a unique state exists with Qa * ~Qb, as on the cycle before Qa was low, and on the next cycle Qb will become high, therefore the state is unique.

Continuing on, you can create 8 unique states using simple 2 input logic combinations.

Now as you've indicated that this is a homework problem, I probably shouldn't just give you the answer, however if you read this thoroughly and the source page, I think you'll understand it simply enough.

Finally, your johnson counter with output decoding would look like this:

And now you've decoded it into 8 states with one-hot encoding.

All of the pictures and knowledge comes from this fantastic and well-explained resource, at Allaboutcircuits

This should provide you with everything you need to know, however if you're still having trouble with how exactly to implement this in VHDL, just ask.

4 flip flop can have 2^4=16 different states. in your problem you only need 8 states. So 8 states does not require 8 gates.

just connect the flip flop as shown in the diagram.

you are working with vhdl so see this johnson counter using structural modeling tutorial