# Designing saturated transistors

I checked the link to this question, but as I was attending a few lectures I was constantly told (also told by some very experienced designers/enthusiasts) that adding an emitter resistor to an NPN transistor reduces chances of saturation and shorting the emitter to the ground drives the transistor to saturation. Is this true? If this is, why is this the case?

The way I see it,

simulate this circuit – Schematic created using CircuitLab

The base emitter loop gives me the equation -

$$V_{in} = I_bR_b + V_{be} + (hfe + 1) I_bR_e$$

$$\dfrac{V_{in} - V_{be}} {R_b + (hfe + 1) R_e} = I_b$$

and for the transistor to be in saturation I would want $V_{ce} < 0.4V$. Hence the equation

$$hfe \, I_b R_c + (hfe + 1) I_b R_e > V_{cc} - 0.4V$$

$$I_b (hfe \, R_c + (hfe + 1) R_e) > V_{cc}-0.4V$$

Using the value of $I_b$ arrived at from the base equation, we get

$$(\dfrac{V_{in} - V_{be}} {R_b + (hfe + 1) R_e}) (hfe \, R_c + (hfe + 1) R_e) > V_{cc} - 0.4V$$

In all this I can't figure out why having $R_e$ shorted or having $R_e = 0$ would be beneficial in any way towards getting the transistor saturated.

When you DON'T have an emitter resistor, the voltage you put on the base pretty much defines the current into the base - it's a forward biased diode so base current starts to rise rapidly above about 0.4V and by the time the base voltage is 0.6V you might be putting 10mA into the base. The transistor will be likely saturated with collector at about 0.2V above emitter.

When you DO have an emitter resistor, as soon as the collector (and emitter) starts conducting current, the emitter voltage rises (due to the emitter resistor) and this "restricts" the current into the base - the rising emitter voltage is "attempting" to turn off the base-emitter junction and now, if you put (say) 2 V on the base, the emitter will be (maybe) at 1.5 V. If the emitter resistor is 100 ohm, the emitter current will be 15mA and this is virtually the same in the collector (largely irrespective of the collector load resistor). But what about base current and Hfe?

Because of the transistor's Hfe, (~200), the base current is going to be about $\dfrac{15mA}{200} = 75\mu A$.

This means the emitter resistor is stopping "foolish" levels of current entering the base and this is a type of negative feedback. It largely prevents saturation with reasonable base voltages.

The way I write it is:

$V_{in} - I_b \cdot R_b - V_{be} - I_e \cdot R_e = 0$

Knowing $I_e = (\beta+1) \cdot I_b$ and re-ordering to solve for $I_b$. So, in the active region, excluding saturation, little-re, and the Early effect:

$I_b \approx \dfrac{V_{in} - V_{be}}{R_b + (\beta+1) \cdot R_e}$

But in saturation, the value of $\beta$ obviously isn't a constant. In fact, it's not an input to the equation. It's an output once you get an approximation using other means.

$I_{b_{sat}} \approx \dfrac{V_{in} - V_{be} - R_e \cdot \left(I_{b_{sat}} + \dfrac{V_{cc} - V_{sat}}{R_c + R_e}\right)}{R_b}$

Or, solving for $I_{b_{sat}}$:

$I_{b_{sat}} \approx \dfrac{V_{in} - V_{be} - R_e \cdot \dfrac{V_{cc} - V_{sat}}{R_c + R_e}}{R_b + R_e}$

(Again, the above is a gross approximation and ignores some important, secondary effects. But it's within the ball park.)

If $R_b >> R_e$, as is often the case, then the denominator is about the same when you "short out" $R_e$. But the numerator get's much larger because a major subtraction (not infrequently close to $\frac{1}{2}V_{cc}$) is removed. So $I_b$ is typically larger by that action. With any appreciable current gain at all, this difference is multiplied substantially and the increased current much more easily overwhelms the somewhat larger drop required (roughly $\frac{1}{2}V_{cc}$, again) across $R_c$ to cause saturation.

Does that make sense?

By the way, the emitter degeneration is often used for reasons other than avoiding saturation. The value of $r_e$, based as it is upon $\dfrac{k \cdot T}{q}$, depends linearly on absolute temperature. A CE configuration without emitter degeneration has its gain similarly dependent upon temperature. Jacking up $V_e$ to about a volt or more above ground makes the gain (and the design itself) much less dependent upon temperature.

• okay. So what I gather is that the main thing it achieves is that it reduces the base current by a difference of approximately Vcc/(2Rb) which when piped by an amplification factor of even lets say 10, goes a long way into stacking the voltage lost due to the aforementioned difference into the Vce junction, hence it sort of spikes the Vce out of saturation, thus making the set-up difficult to saturate. Am I getting it right?? – ubuntu_noob Mar 4 '14 at 14:12
• I don't recall anyone expressing that perspective when considering $R_e$. It's there to reduce the effects of temperature on predictability of the design and gain in the face of temperature variations (ambient from 0 to 45 C, or from additional heating effects on the BJTs.) If you want saturation, you design for it. If you don't want saturation, you also design for that. But one doesn't usually design-in $R_e$ thinking, "Well, I'll just stick a rough value here so my design will be a little better avoiding saturation." But I admit my design experiences are limited. – jonk Mar 4 '14 at 22:09
• okay. How else, do you design for saturation? Is there any thumb rule or so relating the resistors across the base, emitter and collector? – ubuntu_noob Mar 5 '14 at 6:43
• For switching like that, if you know your collector current is a small signal BJT level of $100mA$, then you want $\frac{1}{10}$ to $\frac{1}{30}$ of that for the base current. If you know your collectur current is a large 2N3055 style level of $5A$ then perhaps $\frac{1}{7}$. The datasheet usually provides a "Collector Saturation Region" region chart with some example curves to read. You get a pretty good estimate from there. – jonk Mar 5 '14 at 8:21
• so generally for small signal BJTs, 10(Rc+Re)<Rb<30(Rc+Re) – ubuntu_noob Mar 5 '14 at 8:27