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I have to generate 2 5-bit random numbers and add them using structural verilog and implement it on FPGA. I have to design LFSR with 5 D flip flops and the 5-bit pseudo random number is given by the outputs of the flip-flops. The 5 flip-flops are connected in serial and the 5th flip-flop is xor-ed with the first.

This is the code I have written so far. I am new to verilog and electrical concepts.

module dff (Q, D, Clock);
 output Q;
 input D;
 input reset;
 input Clock;

 reg Q;

 always @(posedge Clock)
 begin
   if (reset)
     Q = 1;
   else 
     Q = D;
 end
endmodule

module DFF_LFSR() ; 
 input D;
 input clk;
 input reset;
 output Q1, Q2, Q3, Q4, Q5;
 reg Q; 

 dff DFF1(Q1^Q5, D, reset, clk);
 dff DFF2(Q2, Q1, reset, clk);
 dff DFF3(Q3, Q2, reset, clk);
 dff DFF4(Q4, Q3, reset, clk);
 dff DFF5(Q5, Q4, reset, clk);
endmodule 
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    \$\begingroup\$ What is your question specifically? Is this code somehow not working? How is the result of this code not matching what you expect? \$\endgroup\$ – The Photon Mar 3 '14 at 19:19
  • \$\begingroup\$ I want to know if the code i have written generates a 5-bit random number. \$\endgroup\$ – user3344978 Mar 3 '14 at 19:23
  • \$\begingroup\$ "Random" is a big call - from your description I would call your implementation more a scrambler and this will eventually repeat. \$\endgroup\$ – Andy aka Mar 3 '14 at 19:31
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    \$\begingroup\$ Output pins cannot be connected as an expression. dff DFF1(Q1^Q5, D, reset, clk); is illegal. Run in a Verilog simulator. \$\endgroup\$ – Greg Mar 3 '14 at 19:33
  • \$\begingroup\$ I made a few changes in the code and was able to synthesize it. The next step i need to do is add the 2 5-bit pesudo-random numbers i generated. So this means i have to design an adder right? I have to design an adder for 1 bit and instantiate it for 5-bits? \$\endgroup\$ – user3344978 Mar 3 '14 at 19:58
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Regarding the general idea of use LFSRs to generate pseudo-random numbers:

As a digital designer, I can say that it's rather common to see LFSRs used to generate "low quality" random numbers. It's a perfectly acceptable approach for many designs.

The biggest problem I see with your fundamental approach is that you want a 5-bit random number, but you're just using a 5-bit LFSR. That design will produce values which are no more random than a counter that counts from 1-31 and repeats--you'll never see the same value twice without first seeing all the other possible values.

The better approach would be to create an LFSR that is much wider than 5 bits, and just take the low 5 bits as your "random" value.

On a side note, Xilinx has an App Note which includes list of taps for various widths of LFSR counters from 3 to 168 bits.

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  • \$\begingroup\$ If i do use just 5-bit random number generator by using the 5-bit LFSR, how do i incorporate an adder module into it so that it adds the 2 random numbers generated? should i create an altogether new source with the adder module and call the lfsr module in it or can i just write an adder module in the lfsr file? \$\endgroup\$ – user3344978 Mar 4 '14 at 17:52
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(Sorry for the answer instead of a comment, I don't have sufficient privilege for a comment yet).

A few notes adding to the other answers:

  • reset needs to be added to the port list for dff
  • it would more conventional to use <= instead of = for the dff assignment.
  • As greg said, Output pins cannot be connected as an expression

Also, it is conventional to connect the final output back to the input instead of having a D input. You want something like :

assign D = Q1 ^Q5;

Also, the way you have it coded, everything will reset to 0, and nothing will ever change after that. So, you also want to reset to a non-zero state.

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