I often need to create a large counter in my projects, mostly to do some timing stuff, which could be to blink an LED every second ect.
I have done this by creating a large counter, as shown in the code below.
sec_proc : process(resety, clk) variable cntr : integer range 0 to 54000000; begin if resety = '0' then cntr := 0; sec_out <= '1'; elsif rising_edge(clk) then if cntr = 54000000 or timein_en = '0' then sec_out <= '1'; cntr := 0; else sec_out <= '0'; cntr := cntr + 1; end if; end if; end process;
The code above often gives me timing issues, timing not kept, I have negative slack. How do you implement such counters effective for synthesis in vhdl?