I often need to create a large counter in my projects, mostly to do some timing stuff, which could be to blink an LED every second ect.

I have done this by creating a large counter, as shown in the code below.

sec_proc : process(resety, clk)
    variable cntr : integer range 0 to 54000000;
    if resety = '0' then
        cntr := 0;
        sec_out <= '1';
    elsif rising_edge(clk) then
        if cntr = 54000000 or timein_en = '0' then
            sec_out <= '1';
            cntr := 0;
            sec_out <= '0';
            cntr := cntr + 1;
        end if;
    end if;
end process;

The code above often gives me timing issues, timing not kept, I have negative slack. How do you implement such counters effective for synthesis in vhdl?

  • \$\begingroup\$ Try a number of smaller counters, when one overflows it can increment the next one. This might allow the synthesis and routing to place the parts more effectively. Alternatively divide down your input clock using a clock manager (if an FPGA). \$\endgroup\$ – David Mar 6 '14 at 11:47
  • \$\begingroup\$ You need to give us much more information. Please copy the exact error/warning messages and tell us what timing constraints you have used in the design. For example, what is the clock frequency? Also, what specific FPGA are you planning to use? \$\endgroup\$ – Joe Hass Mar 6 '14 at 11:52
  • \$\begingroup\$ I was hoping for a more general implementation method, such as David is proposing. I have used a clock constraint on the clk net, setting it to 54MHz. \$\endgroup\$ – JakobJ Mar 6 '14 at 12:27
  • \$\begingroup\$ What FPGA? In a relatively modern FPGA I'm surprised that a counter like that can't meet 54MHz. \$\endgroup\$ – Martin Thompson Mar 7 '14 at 10:46
  • \$\begingroup\$ I'm using the Igloo Nano fpga from Microsemi, I have a lot of components, so my fpga flash is about 80% full. I guess this is why the route and placer have a harder time placing the logic. \$\endgroup\$ – JakobJ Mar 7 '14 at 13:41

Instead of a single 26-bit counter, you should set up multiple shorter counters. For example, you could use a 13-bit counter to divide by 5400, which would give you pulses at 10 kHz, and a second 14-bit counter to divide by 10000, which would give you your 1-Hz pulses.

  • 2
    \$\begingroup\$ Additionally, using a "carry" out of a counter, that will add one high-speed clock (or propagation delay) worth of latency to the end of the counter, but that typically isn't a problem. Do you ever need to read the entire counter value as one, and compare it to a 26-bit constant value? That may be harder if you use cascaded counters. The main problem is that a counter is kind-of like an adder, and you get the "cascading carries" delay. Although many FPGAs have counters as part of macro blocks, they probably aren't as wide as 26 bits. \$\endgroup\$ – Jon Watte Mar 6 '14 at 18:55

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.