I went through a VHDL sample code for memory management. In that data from a 32 bit register was directly moved into a 8 bit register. My doubt it is how this data movement can happen? Is there is any default condition for VHDL for such data transfer?
The default behavior is to match up the bit indices, so if you have
signal reg32 : bit_vector(31 downto 0); signal reg8 : bit_vector(7 downto 0); reg8 <= reg32;
it is equivalanet to
reg8(7 downto 0) <= reg32(7 downto 0);
However, any decent VHDL compiler should give you at least a warning about the width mismatch.