I went through a VHDL sample code for memory management. In that data from a 32 bit register was directly moved into a 8 bit register. My doubt it is how this data movement can happen? Is there is any default condition for VHDL for such data transfer?

  • \$\begingroup\$ The question is not entirely clear. In general, VHDL is not big on things happening by "default conditions" and very big on stating exactly what you want to happen. \$\endgroup\$ – Brian Drummond Mar 6 '14 at 13:56

The default behavior is to match up the bit indices, so if you have

signal reg32 : bit_vector(31 downto 0);
signal reg8 : bit_vector(7 downto 0);

reg8 <= reg32;

it is equivalanet to

reg8(7 downto 0) <= reg32(7 downto 0);

However, any decent VHDL compiler should give you at least a warning about the width mismatch.

  • \$\begingroup\$ IIRC, assignments between slices of different sizes are not legal, so the code would be in error (not simply a warning). Also, I believe the correct behavior would be for the VHDL tool to ignore the indices, and make the assignments between elements in left-to-right order. Would you confirm it? \$\endgroup\$ – rick Oct 26 '14 at 17:59

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