I am studying synchronous digital circuits and I have come to the conclusion that master slave flip flops are edge triggered? Is my study correct? If master slave versions ARE edge triggered, why do we need separate edge triggered flip flop versions like the edge triggered D flip flop (the non- master slave configuration)?
Master-slave just a way of combining two gated or level triggered latches together to form an edge-triggered flip flop. A master-slave D flip flop is just one way that you can build a D flip flop.
The idea behind a master-slave flip flop is that you can connect two latches back to back so the 'master' latch will update while the clock is low and the slave latch will update while the clock is high. In this instance, when the clock transitions from low to high, the current state at the input of the master flip-flop is captured and propagated to the output. This functionality forms a D flip-flop.
However, master-slave is not really the only way to build a D flip-flop. It is possible to build both dynamic gates that use capacitance to hold the value during the clock transition, allowing the gate to be much smaller and simpler. It is also possible to build the same functionality with some inverters and transmission gates. It depends on what level of the design you are working at. If all you haveis logic gates, you probably need to build a master-slave flip-flop. However, if you are working at the transistor level, then you can build something more optimized.
tl;dr: a master-slave flip flop IS a D type flip-flop, but it is ot the only way to make one.
Because, Normal latches are sensitive to data changes during the clock input, So a change in data will reflect in a change in the output. therefor you have the MS Flip flops, they read the input value on the rising clock edge, and output the data on the falling clock edge. and there for the data will not change once it has been set during the rising edge.
In a clock pulse the high state can be there for X amount of time and while the high state is active a Non-MS FF will change its output when teh input data changes and this can happen multiple time in a CLK high, A rising Edge only happens once in every clock pulse so this is why the data will only change once every clock pulse, and this is why there are MS flip flops along with normal Flip Flops.
A conventional J-K master-slave flip-flop is not edge-triggered, because while the clock input is high, pulses on the J or K inputs will affect the master, and can affect the Q (and not-Q) state that results on the next clock falling edge. Conventional J-K master-slave flip-flops are properly called "pulse-triggered" or "level-triggered".
On the other hand, a D master-slave flip-flop is edge-triggered, because the D input and its complement always drive the master stage in complementary fashion, even while the clock is high.
This is somewhat hard to explain without going into a detailed analysis.
True edge-trigered JK flip-flops are usually implemented internally using an edge-triggered D flip-flop, with appropriate combinatorial logic between Q (or not-Q), J, and K to feed the internal D input. For examples of that, see the datasheets for the 74LS109 and 74HC109. The 74LS109 uses a variant of the three S-R latch edge-triggered D FF design of the 7474, while the 74HC109 uses an edge-triggered master-slave D FF.