The wires in the differential pairs will be routed very close to each other, allowing signals from one wire to couple onto the adjacent wire. Most of the crosstalk is likely to be capacitive. Think of the two wires as plates in a capacitor. A sudden change in one wire will 'leak' onto the other one. Coupling like this is frequency-dependent. DC will not couple at all. Slow edges may couple a little bit. Very fast edges can couple very significantly. If you put a square wave with very fast edges on one wire, the adjacent wire will get sharp positive and negative going edges, followed by exponentially decaying slopes. The positive peaks correspond to the rising edge of the square wave, the negative peaks correspond to the falling edge.
If you are forced to use differential I/O as single-ended I/O, there are a few considerations. If the overall trace length is short, the effects may be so small they can be ignored. If the trace is long, then you might need to do something mitigate the crosstalk. One easy solution is to only use one wire out of each pair. The other wire can be driven to ground, or the two can be driven at the same logic level. This reduces the number of available I/O by a factor of 2, however. Another possibility is to decrease the slew rate of the output I/O pins. Xilinx FPGAs have several selections for drive strength and slew rate. Turn the slew rate to the lowest setting, quietio. Also try turning down the drive strength. You can also try turning on the 50 ohm source impedance as this will limit how much current can flow out of the pin. Setting the 50 ohm source impedance should also limit reflections off of the FPGA I/O pins, as signals in an unmatched system can bounce around for some time, requiring more time to stabilize.
It's hard to say how fast you would be able to run without significantly more information about what you're trying to do. Unfortunately, I am not familiar enough with the board to be able to give you any estimates. It looks like the traces could be pretty short, though.
To get an idea of how much crosstalk you can get on a pair, set the FPGA to hold one at a constant level (GND or VDD) and toggle the other one at a few MHz. Set the slew rate to fast on the IO pin. Then connect a scope to the 'victim' pin and measure the height of the peaks. If it's much less than VDD, then it might not cause any problems.