Lets say there is a circuit that takes 3 bit input and produces an odd parity bit output.So I have arrived at the following truth table.

      A    B   C    Output(D)
1     0    0   0       1
2     0    0   1       0   
3     0    1   0       0
4     0    1   1       1
5     1    0   0       0
6     1    0   1       1
7     1    1   0       1
8     1    1   1       0

As an expression this comes to

A'B'C' + A'BC+ AB'C+ ABC'

So far so good. My problem begins now.

Now I am asked to design a second circuit which takes the three inputs and one output of the first circuit and output 0, if the odd parity is satisfied.

I have to put up a truth table and use Karnaugh map to design the boolean expressions for each of the output bits. But as per my understanding taking the 3 input ad one output bit from the previous circuit as inputs to the new circuit will always yield a 0.

But had that been the case, the question of using karnaugh map would not have been asked in the first place.

What am I missing or misunderstanding in the question ?

Here's the original question, just in case I have understood it wrong. enter image description here

  • \$\begingroup\$ What does the problem statement mean by and outputs 0 if the odd parity is satisfied ? \$\endgroup\$
    – tcrosley
    Mar 9, 2014 at 23:16
  • \$\begingroup\$ That is the exact cause of my confusion. Unfortunately there are no professors to clarify that :( \$\endgroup\$
    – bhaskarc
    Mar 10, 2014 at 8:24

2 Answers 2


As far as I know, the first circuit is basically 2 cascaded XOR gates which outputs 1 if the the no of high inputs are odd. Hence circuit 1 outputs 1 when odd parity is satisfied. If you want circuit two to be a circuit whose output is zero when odd parity is satisfied then just add a not gate to the output of circuit 1.


simulate this circuit – Schematic created using CircuitLab

Is this what you are looking for? I bet you can simplify circuit 2 by using boolean algebra when u go for AND-OR-INVERT implementation.

  • \$\begingroup\$ Nice to know...:) You can find me at [email protected]. Not a word more here or else the community moderators will start throwing bombs at us...;) \$\endgroup\$
    – Ghosal_C
    Mar 10, 2014 at 16:18

Parity is used for error detection. The first part of the question asks you to generate the parity bit. You can use two cascaded XOR gates to generate the output of the first circuit.

two XOR gates
(source: lizarum.com)

Now, it asks you to test the 3 inputs and 1 output (A, B, C, and F above) for odd parity. This should always be true, except when an error occurs. Errors occur for numerous reasons which I won't go into. The point is the second circuit is an error detector. You can do the same strategy to test for odd parity. Pass the four inputs through 3 XOR gates, as shown below. You'll have to invert the output as well (not shown). In the image, replace 'D' with 'F' and invert the output. This circuit should always produce 0, but if an error flips one of the input bits, it'll produce a 1.

three XOR gates

Finally, the question says to only use AND, OR, and NOT gates. Just replace each XOR gate with its equivalent circuit using those gates. An example is shown below. I'm sure there's a more optimal solution, but this suffices to answer the question.

XOR gate breakdown


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