I'm trying to synthesize an Altera circuit using as few logic elements as possible. Also, embedded multipliers do not count against logic elements, so I should be using them. So far the circuit looks correct in terms of functionality. However, the following module uses a large amount of logic elements. It uses 24 logic elements and I'm not sure why since it should be using 8 + a couple of combinational gates for the case block.

I suspect the adder but I'm not 100% sure. If my suspicion is correct however, is it possible to use multipliers as a simple adder?

module alu #(parameter N = 8)
    output logic [N-1:0] alu_res,
    input [N-1:0] a,
    input [N-1:0] b,
    input [1:0] op,
    input clk

wire [7:0] dataa, datab;
wire [15:0] result;

// instantiate embedded 8-bit signed multiplier
mult mult8bit (.*);

// assign multiplier operands
assign dataa = a;
assign datab = b;

    unique case (op)
        // LW
        2'b00:  alu_res = 8'b0;
        // ADD
        2'b01:  alu_res = a + b;
        // MUL
        2'b10:  alu_res = result[2*N-2:N-1]; // a is a fraction
        // MOV
        2'b11:  alu_res = a;

  • \$\begingroup\$ This is a migrated question from stackoverflow.com/questions/22304059/… \$\endgroup\$ – Greg Mar 10 '14 at 15:41
  • 1
    \$\begingroup\$ Your existing design is using 16 logic elements to implement the 8-bit 4:1 mux represented by the case statement, and 8 logic elements (in conjunction with dedicated carry hardware) to implement a + b. It really doesn't get much better than that. \$\endgroup\$ – Dave Tweed Mar 10 '14 at 15:59
  • \$\begingroup\$ I'll copy my comment from StackOverflow: "unique for synthesis means parallel_case and full_case. Try it with priority (only full_case) instead. Also try it without a keyword in front of the case statement." \$\endgroup\$ – Greg Mar 10 '14 at 16:41
  • \$\begingroup\$ From my experience, parallel_case tends require more logic gates but provides a faster data path. \$\endgroup\$ – Greg Mar 10 '14 at 16:43
  • 2
    \$\begingroup\$ Style point: if you used localparam [1:0] LW=2'b00, ADD=2'b01, MUL=2'b10...; you'd find the output mux code self documenting (or an SV enum) \$\endgroup\$ – shuckc Mar 11 '14 at 14:26

Use the Altera "Technology Map Viewer" if you want to see exactly how/where those 24 elements are being inferred.

I'm not certain what technology you targeted. For a StratixV it uses 16 regs and 1 DSP slice and if you need it you'll get the next register stage for free from the mux output.

RTL Viewer

RTL view

Technology/resource view enter image description here

You can see the logic elements are used one per bit for the output mux and one per bit for the adder, with the DSP cell highlighted.

You might be able to pack the whole thing into a single SV DSP cell using the various mode bits (pre adders for a/b, set mult stage to x1) to avoid the output mux, but the whole thing is moot on that kind of device!

  • \$\begingroup\$ Thank you for this. I'm relatively new to Quartus and there are many features I've yet to uncover. I'll look into this. \$\endgroup\$ – geft Mar 11 '14 at 16:54

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.