I am trying to integrate a third-party IP core, which is given in form of an .ngc netlist file and a corresponding .vhd file with only the entity declaration, into my design. The IP core was synthesized with Xilinx ISE.
I have instantiated the core in my design and connected all external signals.
However, I fail at finding the correct point in the command line tool flow of Xilinx, where I can include the netlist file such that it is used during translation(ngdbuild). At the moment I only pass the path where the .ngc file is located to ngdbuild via the -sd flag and do the same for the .vhd file when calling xst.
Up to now, in the final design, the IP core is missing. The synthesis report shows that there is a warning "WARNING:HDLCompiler:373 - "" Line 43: Entity does not have an architecture", and the synthesis summary shows that no logic has been inferred for this module. (This is to be expected since the netlist file should be used instead of synthesising any logic).
Is there a naming convention that has to be met so ngdbuild can link the .ngc file to the correct entity (netlist file and entity have different names) or what is it that I am missing completely?