Is impedance matching a requirement for CAT-5e traces?

Question

I'm building a patch-board for CAT-5e cables, whereby any pin can be re-wired to any other by a set of jumper cables. This is for testing black-box systems where weird things have been done to Ethernet sockets in order to make it difficult for someone to just walk up and plug in a laptop.

I'm in the PCB design phase, and have the following design in mind:

Here's the design I have in mind:

The board is using 0.254mm traces, and the total length of each trace is no more than 25mm. I've alternated the traces on each side of the board to increase clearance between them, and hopefully the PCB itself should provide a little insulation against EM leakage.

I'd like to know if impedance matching is going to be an issue on a standard 10/100 Ethernet link, across this kind of design. Obviously the outer traces are currently about 50% longer than the middle one.

Any other recommendations on improving the design would also be welcome.

Answer 1

About trace length matching:

IEEE 802.3 specifies propagation delay and not distance (see 23.6.2.4 Delay from IEEE standard section 2). It says that you should have a maximum propagation delay of 570ns for your entire link and also propagation speed per meter should not exceed 5.7ns/m (thus the 100 meter common "limit").

But you are not concerned by these specs (just a reminder, in case you have a long link).

23.6.2.4.3 Difference in link delays
The difference in propagation delay, or skew, under all conditions, between the fastest and the slowest simplex link segment in a link segment shall not exceed 50 ns at all frequencies between 2.0 MHz and 12.5 MHz. It is a further functional requirement that, once installed, the skew between all pair combinations due to environmental conditions shall not vary more than ± 10 ns, within the above requirement.

You should retain that the maximum skew allowed on your whole link is around 10% of the maximum propagation delay (570 ns). As you are designing a custom adapter, we will take large margins to simplify computations and consider your adapter is equivalent to 1 meter of link.

So the maximum propagation delay allowed for your segment is 1/100 of 570ns = 5.7ns. The allowed skew between pairs is 1/100 of 50 ns = 500 ps.

Given your routing specs, the propagation delay of the signal is around 50 ps/cm. So with a 500 ps allowed skew delay, you can have a length difference of 10 cm.

No worries here.

Also, about EM leakage, 100 Mbits Ethernet signal frequency is 12.5 MHz, even if it is rise time equivalent frequency that matters, you don't have to worry to much if you are following advices given here by Dzarda and dextorb

Answer 2

Your trace impedance will be mainly controlled by your board stack-up parameters, not, interestingly enough, the trace length.

If you're interested, play around with a PCB calculator for a bit. Saturn PCB Design, Inc. provides a nice toolkit.

You will need to know some parameters of your stack-up in order to calculate your differential impedance. You will want to target a \$Z_{diff}\$ (differential impedance) of 100Ω for Ethernet.
Take notice there is a tolerance window; it doesn't have to be exact. How aggressive you want to be depends on the application. In some situations, perhaps you can get away with +/-20%, and maybe sometimes you can't.

Also, you'll want to route the RX+/- and TX+/- pairs together, on the same layer, as they are differential pairs.

Length-matching, while related to signal integrity, is a different matter. Just keep the traces short like you have and you will be fine.

Answer 3

I wouldn't worry about it too much. Of course there are standards saying that you need to maintain \$100\Omega\$ differential impedance, also to keep your differential pairs length-matched to 50 mils, etc...

Just a tip:

I'd stick with 45° turns. Or if you need to get fancy, you can use round corners.

If you require as much reliability as you can get, match your lengths using meanders