I am working with the I2S audio protocol in one of my projects and I'd like to use it in one of my final projects for a class of mine. Quite honestly though, I don't entirely understand the MCLK line. You'd think, "Oh that just stands for Master Clock" and you might be right but since everything has to do with audio and sampling rates, I get confused.

I'm using the CS42436 in software mode: in short it takes in 3 signals (that I'm questioning).

MCLK - Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.

SCLK - Serial Clock (Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs

FS - Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format.

Can somebody explain how to use these clock signals in reference to this picture?

I2S Protocol

I know the middle signal is the serial clock, but the other two I don't understand at all.


The top signal is Frame Sync (FS). FS is used to indicate whether the audio is for the left or right channels. Don't think of them as "left" and "right" though, those are just arbitrary names. Think of them as channel 0 (FS clear) and channel 1 (FS set), time-division multiplexed onto a single communications link.

The bottom signal is the serial data that is being clocked into(?) your MCU.

MCLK is not visible in that diagram. It is the clock that is used by the audio codec (in your case, a CS42436) to time and/or drive its own internal operation. It is a relatively high frequency; a common value is 256*Fs (where Fs is the sample rate, e.g. 44.1kHz). Values in the range of 10-60MHz are pretty typical.

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    \$\begingroup\$ It really depends on the codec and your accuracy requirements. In your case, from my brief glance at the CS42436 datasheet (p33 s5.4.1), it looks like you need to supply it with either 256*Fs or 512*Fs to get it to function correctly. You'll need to examine your MCU's datasheet to see if it has a PLL that it can use to supply the I2S MCLK with a precisely tailored frequency to suit the codec's needs (e.g. 11.2896MHz for 44.1ksps @ 256*Fs). \$\endgroup\$ – markt Mar 12 '14 at 1:49
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    \$\begingroup\$ > Why does MCLK exist? It's the clock input of the digital circuitry (DSP or whatever there is) of the DAC. Some DACs require it, some make it themselves, some can accept external oscillator on PCB. \$\endgroup\$ – PkP Dec 20 '16 at 7:07
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    \$\begingroup\$ @endolith, you typically cannot choose freely which one you use. Since two clocks are never the same, both ends of the connection must use the same clock to derive the sample clock. If one end consumes samples at 96000.1 Hz and the other end produces them at 96000.2 Hz you will have pops, clicks and horribilities in the sound. So the first thing to do is to consider who is the data master, who is the data slave, who is the clock master and how does the clock slave derive the sample clock from clock master clock. All variations are possible in i2s, see spec for "i2s enhanced" \$\endgroup\$ – PkP Mar 2 '17 at 9:21
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    \$\begingroup\$ @endolith, the best arrangement is the one where the analog interface is the clock master, e.g. in case of DAC the DAC is the clock master and the microcontroller generates samples to match the clock from the DAC. And in the case of ADC, the ADC is the clock master and produces samples and the MCU consumes the samples at the ADC rate. These two rates are not the same, so in case of having both ADC and DAC, you will need to either set one of them to be the clock slave or do sample rate conversion in a DSP. 96.00001 kHz is not the same sample rate as 96.00002 kHz! \$\endgroup\$ – PkP Mar 2 '17 at 9:24
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    \$\begingroup\$ @endolith, you're right. It's a tradeoff between EMI and the sound quality, as clock reconstruction can never be perfect. If you're making the PCB, connect the trace anyway, then decide if you want to use it or not. I'd use the 12MHz trace and only optimize it away if the EMI becomes a real problem. I also suggest that you add a footprint for some filter component to the trace (perhaps equip it with short circuit in the beginning). \$\endgroup\$ – PkP Mar 2 '17 at 14:27

Serial clock is not 256 * Fs, Serial clock is your sampling freq (Fs) * # of bits / channel * # of channels. for ex, 2 channels for Stereo and 1 channel for Mono.

  • \$\begingroup\$ So it's a bit clock (BCLK)? \$\endgroup\$ – endolith Nov 4 '16 at 15:39
  • \$\begingroup\$ For this chip, SCLK actually is mandated to be 256 * Fs. But that would not be the case historically. \$\endgroup\$ – Chris Stratton Apr 27 '18 at 14:02

The Master clock generates the timing of the i2s stream, so bitclock and frame sync signals are derived from it. It can be derived by a Crystal connected to the DAC (i2s-master). Or, it may be the CPU providing a MCLK to the DAC, that is still master.


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