I have the following setup:

An FPGA eval board has a daughterboard with pin headers connected to it. From these headers I have connected 16 ~10 inch 24-gauge wires to feed a bus to a TI OMAP-138 Microcontroller eval board's built int connectors wired to its GPIO pins. I am generating audio waveforms (speech) on the FPGA and sending it across the bus at a constant 8Ksps. The FPGA's clock is 30 MHz and the Microcontroller is 300MHz. The FPGA also sends a clock signal I use to sample the data.

The problem is when I display the data from the Microcontroller I see major distortion in the read audio (I get it from a memory dump). I also read the data from the FPGA with a logic analyzer from a Mictor connector on the same daughterboard and that signal is not distorted.

Here is a picture of the two (not quite aligned but close enough to see).

enter image description here

I have no experience with dealing with transients like this. At these speeds is this kind of distortion expected or is it likely a problem with how I am reading data with the Microcontroller?

  • \$\begingroup\$ By the way I am using professional eval boards from Xilinx and TI. None of the PCB design is my own. \$\endgroup\$
    – ballaw
    Mar 13, 2014 at 0:16
  • \$\begingroup\$ I have probed the MIcrocontroller end of the wires with an Oscope and the signals look clean. \$\endgroup\$
    – ballaw
    Mar 13, 2014 at 0:18
  • 1
    \$\begingroup\$ How do you have the grounds of the 2 eval boards tied together? You need a good low inductance ground connection between the two boards, a single ground wire probably isn't enough. \$\endgroup\$
    – John D
    Mar 13, 2014 at 0:32
  • 1
    \$\begingroup\$ With regard to the sample clock that runs from one system to the other: Are you changing the data on one edge of the clock and then sampling it on the opposite edge? \$\endgroup\$
    – Dave Tweed
    Mar 13, 2014 at 1:08
  • \$\begingroup\$ I am changing the data on the positive edge and sampling on the negative edge. \$\endgroup\$
    – ballaw
    Mar 13, 2014 at 17:28

1 Answer 1


This has to be a protocol error between FPGA and MCU. Your low-level AC signal (audio) from the FPGA is being mis-read (somehow) by the MCU. The noise looks like incorrect value of the sign bit appearing as large impulses on the decoded signal.

As Dave Tweed says, you don't want the MCU to be reading the signal while the FPGA is updating it. Are you reading all the GPIO pins with a single instruction? I'm guessing not.

You might want to bombproof this transfer with a handshake from FPGA to MCU. Update the audio sample then assert a Req signal. Wait for the MCU to assert an Ack signal, retract Req, then wait until MCU retracts Ack (and the next sample is ready) before updating the signal again.

In the MCU, only access the audio data when Ack is 1.

  • \$\begingroup\$ The problem with handshaking is the input is streaming audio so it can't be halted. Originally I was reading each pin with a separate instruction but I changed it to two memcpys. I still don't see why that would be a problem since the data is being streamed at 8KHz and the microcontroller clock is 300MHz. I have a clock signal from the FPGA I am using to synchronize the transfer. The data changes on the positive edge and is sample don the negative edge. \$\endgroup\$
    – ballaw
    Mar 13, 2014 at 16:59
  • \$\begingroup\$ The entire handshake ought to take place within much less than that 8kHz sample period so in practice there would be no halt. \$\endgroup\$
    – user16324
    Mar 13, 2014 at 18:21
  • \$\begingroup\$ Well, you guys talk about this as if it is a really high speed problem, 8khz sample rate can be easily buffered using a FiFo for the input/output where the handshake state machine takes care of the communication with the OMAP. I bet you can run that part at 100MHz if you want, so no problem with 8k/s sample! \$\endgroup\$
    – FarhadA
    Mar 17, 2014 at 14:23

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