I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the two to make an 8 bit multiplier accumulator, but can't think of a good way to synchronize all the signals. As in, how do I make my adder wait for 8 clock cycles until the product is given, before it performs addition with the previous result?
The accumulator result has to be first initialized to zero, which then changes every 8 clock cycles as soon as the correct product is available. Also I want the code to be synthesizable. Please suggest a way of doing this.
This is what I have done so far:
module mac_abacus (result, x, y, clk, reset); output [16:1] result; input [8:1] x, y; input clk, reset; wire [16:1] product; wire carry, cin; reg [16:1] prod_bus, prev_sum; wire [16:1] sth; ab_mac abmacus (product, x, y, clk, reset); //this is the multiplier //when reset=1, prev_sum=0, prod_bus=0,result=0 //when reset=0, prev_sum=result(i.e the previous result), //prod_bus=product(shd change every 8 clock cycles alongwith the product) condsum16 csummer (result, carry, prod_bus, prev_sum, cin);//this is the accumulator //so, effectively when reset=0, result shd hold its value until 8 clock cycles when the new product appears endmodule