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I have designed an 8-bit multiplier in Verilog which takes a maximum of 8 clock cycles to give the product. I have also coded a 16 bit adder based on combinational logic. I now want to integrate the two to make an 8 bit multiplier accumulator, but can't think of a good way to synchronize all the signals. As in, how do I make my adder wait for 8 clock cycles until the product is given, before it performs addition with the previous result?

The accumulator result has to be first initialized to zero, which then changes every 8 clock cycles as soon as the correct product is available. Also I want the code to be synthesizable. Please suggest a way of doing this.

This is what I have done so far:

    module mac_abacus (result, x, y, clk, reset);
    output [16:1] result;
    input [8:1] x, y;
    input clk, reset;
    wire [16:1] product;
    wire carry, cin;
    reg [16:1] prod_bus, prev_sum;
    wire [16:1] sth;


    ab_mac abmacus (product, x, y, clk, reset); //this is the multiplier
    //when reset=1, prev_sum=0, prod_bus=0,result=0
    //when reset=0, prev_sum=result(i.e the previous result), 
    //prod_bus=product(shd change every 8 clock cycles alongwith the product)

    condsum16 csummer (result, carry, prod_bus, prev_sum, cin);//this is the accumulator
    //so, effectively when reset=0, result shd hold its value until 8 clock cycles when the new product appears
    endmodule
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  • \$\begingroup\$ Why don't you share the code you have so far? Then we'll be able offer suggestions that fit with it, following your interface conventions and coding style. \$\endgroup\$ – Dave Tweed Mar 13 '14 at 4:39
  • \$\begingroup\$ well, I am not sure if i should be posting the code because it's rather long, especially the one of the multiplier \$\endgroup\$ – titan Mar 13 '14 at 4:56
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Add a counter and assign prev_sum to result on every eighth clock.

always @(posedge clk) begin
  if (reset) begin
    prev_sum <= 16'h00;
    counter <= 3'b000;
  end
  else begin
    if (counter == 3'b111) begin
      prev_sum <= result;
      counter <= 3'b000;
    end
    else begin
      counter <= counter + 1'b1;
    end
  end
end
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  • \$\begingroup\$ This this answered your question, please accept it. IF not, please clarify what you still have issues with. \$\endgroup\$ – Greg Mar 31 '14 at 23:13

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