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I'm reading a VHDL design and I came across the syntax in the architecture that looks like:

    x_out <= x_in(15) & x_in(6) & x_in(19) & x_in(20) & x_in(28) & x_in(11) & 
                x_in(27) & x_in(16) & x_in(0) & x_in(14) & x_in(22) & x_in(25) & 
                x_in(4) & x_in(17) & x_in(30) & x_in(9) & x_in(1) & x_in(7) & 
                x_in(23) & x_in(13) & x_in(31) & x_in(26) & x_in(2) & x_in(8) & 
                x_in(18) & x_in(12) & x_in(29) & x_in(5) & x_in(21) & x_in(10) & 
                x_in(3) & x_in(24);

where x_out and x_in are std_logic_vector(31 DOWNTO 0). Could this be written like so:

x_out(0) <= x_in(15);
x_out(1) <= x_in(6);
x_out(2) <= x_in(19);   
x_out(3) <= x_in(20);
x_out(4) <= x_in(28);
x_out(5) <= x_in(11);
x_out(6) <= x_in(27);   
x_out(7) <= x_in(16);   
x_out(8) <= x_in(0);
x_out(9) <= x_in(14);
x_out(10)  <= x_in(22); 
x_out(11)  <= x_in(25);
x_out(12)  <= x_in(4);
x_out(13)  <= x_in(17);
x_out(14)  <= x_in(30); 
x_out(15)  <= x_in(9);  
x_out(16)  <= x_in(1);
x_out(17)  <= x_in(7);
x_out(18)  <= x_in(23); 
x_out(19)  <= x_in(13);
x_out(20)  <= x_in(31);
x_out(21)  <= x_in(26);
x_out(22) <= x_in(2);   
x_out(23) <= x_in(8);
x_out(24) <= x_in(18);
x_out(25) <= x_in(12);
x_out(26) <= x_in(29);  
x_out(27) <= x_in(5);
x_out(28) <= x_in(21);
x_out(29) <= x_in(10);
x_out(30) <= x_in(3);   
x_out(31) <= x_in(24);

Or in the first example is x_out(31) <= x_in(15); and so on?

Also in a VHDL design which of the 2 methods are preferred?

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    \$\begingroup\$ In the single element assignments to x_out you have the order reversed. The first one should be x_out(31) if it is declared (31 downto 0) to match the x_out <= x_in(15) & x_in(6) & x_in(19) &... order. The leftmost element of x_out is 31. The leftmost element of the right hand side expression is x_in(15). \$\endgroup\$
    – user8352
    Mar 13, 2014 at 18:27

3 Answers 3

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A cleaner alternative, preventing the mistake illustrated by the question :

Use named rather than positional association.

x_out <= (31 => x_in(15),
          30 => x_in(6),
          29 => x_in(19), 
          ...
          1  => x_in(3),
          0  => x_in(24));
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1
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Personal preference OR design team schemas

My personal preference would be to style #2 as it is easier to read and change

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  • \$\begingroup\$ In example 1 given is x_out(31) <= x_in(15); or is it x_out(0) <= x_in(15);? Thats what Im struggling with the syntax. \$\endgroup\$
    – Dean
    Mar 13, 2014 at 16:56
  • \$\begingroup\$ There's a third way to express the permuted assignment, as an aggregate target ( x_in(31) & x_in(30) &...). I'd personally prefer the original way but would line up the occurrences of x_in vertically in the right hand side expression. It cuts down on all the assignment noise. \$\endgroup\$
    – user8352
    Mar 13, 2014 at 18:43
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Brian's solution is probably the best alternative. Anyway, here's a compact solution in case you want to save a few lines.

constant permutation_indexes: integer_vector := (
    15,  6, 19, 20, 28, 11, 27, 16,  0, 14, 22, 25,  4, 17, 30,  9,
     1,  7, 23, 13, 31, 26,  2,  8, 18, 12, 29,  5, 21, 10,  3, 24
);
...        
permutation: for i in x_out'range generate
    x_out(i) <= x_in(permutation_indexes(i));
end generate;
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