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I need to design a circuit that generates the voltage waveform shown in the Figure 1 when an input voltage is applied as shown in Figure 2. Figure 1 and Figure 2 are in the second link below. Only Opamps and RC circuits are available and LTspice IV must be used. I am sophomore at electrical engineering and I was trying during the last 8 hours but I just get closed as in the first link below that contains the .asc file that I worked on and that you can work. I will be glad if you help me to complete the circuit.

https://www.dropbox.com/s/tbs3i1e6ckk1c09/Draft10.asc

enter image description here

figures 1 and 2 http://oi57.tinypic.com/ih5v95.jpg

Sincerely

Thank you who participated by answering this question. The given information is really helpful. I designed the circuit as given in the link below. https://www.dropbox.com/s/gl48itw82hu4l4v/Yeni%20Microsoft%20Office%20Word%20Belgesi.docx However, this design is still include too much staff. Can anyone design a better one and share to us?

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  • \$\begingroup\$ Even the voltage level of output waveform is coming to 15.0V volt, which I think should be at 12.0V as per the OP.And by the way what is lower voltage of output waveform 0V or ?? \$\endgroup\$ – AKR Mar 18 '14 at 4:27
  • \$\begingroup\$ The lower voltage is very important, for input and output waveform. Along with that, I feel single supply opamp should be used, what you have in .asc file is dual supply opamp and the solution lies in "inverting amplifier" and "buffer" using opamp. \$\endgroup\$ – AKR Mar 18 '14 at 5:49
  • \$\begingroup\$ The integrator stage around U1 will drift away, tame it with a resistor in parallel of the capacitor. Several resistors are impractically low (say < 100Ω) \$\endgroup\$ – jippie Mar 18 '14 at 6:46
  • \$\begingroup\$ Invert. Integrate. Rectify. This gives the delay from t0 to t0+2 when the ramp is negative. Assume input is +- (I see a note that says AC). \$\endgroup\$ – C. Towne Springer Mar 18 '14 at 7:58
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You need to create a new pulse from the original pulse. The new pulse should start from zero and rise to a positive voltage when t = t0 + 2. At t= t0 + 6, the pulse should complete and return to zero.

This allows you to use an integrator between the start of the new pulse and t = t0 + 4. At t = t0 + 4 the integration process should be suspended (or halted) until the pulse ends at t = t0 + 6. Thereafter, integration is restored and the output ramps down: -

enter image description here

That's how I'd do it - good luck.

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Invert. Integrate. Rectify. Input pulse must be AC or dual supply that goes from one polarity to the other.

Imagine the ramp starts at t0 and is negative. You can see why there is a delay. Rectify to get zero when the ramp is not positive. Use an op-amp "ideal" rectifier so there is no 0.7V drop from a diode.

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Consider the output waveform as the output of an integrator. To produce this output, you would need an input waveform that's zero for 2 seconds, then positive for 2 seconds, zero for 2 seconds, negative for 2 seconds, and finally zero.

Such a waveform could be created by summing a series of four individual step waveforms:

integrator input = step (t-2) - step (t-4) - step (t-6) + step (t-8)

A single delayed-step waveform can be constructed using the combination of an integrator and a comparator. Four copies of this sub-circuit would produce the four step waveforms needed above.

Is this enough of a hint?

Note that we need to assume that these are not ideal opamps with an infinite output voltage range, but rather real opamps that have a finite output swing that is determined by their supply voltages. Otherwise, we can't meaningfully use an opamp as a comparator.

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  • \$\begingroup\$ Thank you for the useful information. I'm done. However, I need to ask that Is there any short way to design this circuit? Due to the fact that the designed circuit will be implemented during the laboratory hours and on a breadboard. It will be hard to construct them on a limited time. \$\endgroup\$ – eosin Mar 18 '14 at 21:35
  • \$\begingroup\$ About the only thing I can suggest is to work out on graph paper ahead of time what your component layout will be for each subcircuit. Then, doing the actual assembly in the lab should be very straightforward. \$\endgroup\$ – Dave Tweed Mar 18 '14 at 21:55
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I agree with Andy. The timing starts with the leading edge. Then there is a 2T DELAY before the output ramps up. After a further delay of 4T the output ramps down. The integrator takes 2T to rise (from 0 to 12V) and 2T to fall. This would mean the time constants or the rise and fall would be equal.

enter image description here

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  • \$\begingroup\$ The integrator won't change slope from adding zero. \$\endgroup\$ – C. Towne Springer Mar 19 '14 at 1:02

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