I am interested in knowing the deterministic and random jitter characteristics of PLLs internal to Stratix V FPGAs. I have looked through the Stratix V handbook but could not find numbers quantifying the jitter of their PLLs.

What are the jitter characteristics of PLLs in Stratix V FPGAs?

  • \$\begingroup\$ You probably won't find this information. If you are interested in low jitter, you will probably have to use external clock or PLL (so the internal PLL doesn't matter). If you just need to know if you can cascade internal PLLs, app notes may help. (e.g. in Xilinx you can cascade two DLLs/DCMs, but a third will lose lock). \$\endgroup\$ – Brian Drummond Mar 19 '14 at 12:38
  • \$\begingroup\$ @BrianDrummond: I found the information. See my answer. \$\endgroup\$ – Randomblue Mar 19 '14 at 12:57
  • \$\begingroup\$ Excellent. Sometimes it's nice to be wrong... \$\endgroup\$ – Brian Drummond Mar 19 '14 at 13:01

Found it! See page 38 of this document.

  • \$\begingroup\$ This is a link-only answer and will become useless when altera decides to move the links around. \$\endgroup\$ – pipe Oct 1 '17 at 20:05

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