# How exactly does this shift-register work? - Fairchild 74HC589

I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589.

I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, although, there is a step that is elluding me:

• According to the datasheet, there is a Serial Load pin (13) and a Read Clock pin (12). Supose I just want to load whatever is in the input latches to the shift-register itself and then simply clock the bits out one by one to the serial output pin. What kind of signal/timing sequence am I looking for?

As I figure it out, the serial load pin should be activated to latch the input pins and then the read clock should transfer from the latches to the shift-register, right?

I need to know this because I'm controlling the SR via a PIC32MX and for now I need to know how I can SET or CLEAR the pins I have connected to the SR so I can then read serially in other PIC32 pin.

Any thoughts?

EDIT:

To help everyone understand my question (hopefully) a bit better, each pin on the shift-register is directly connected to a pin in the PIC32. For instance:

    #define READ_CLK                PORTFbits.RF0

#define SR_CLK                  PORTEbits.RE3
#define SR_CLK_TRIS             TRISEbits.TRISE3

#define SDI_BUS                 PORTEbits.RE2
#define SDI_BUS_TRIS            TRISEbits.TRISE2


This way, by SETing or CLEARing each signal, I can enable/disable the pins in the shift-register.

In the end, the idea would be to read in the PIC's SDI_BUS pin whatever comes out of the shift-register's QH (pin 9) output.

EDIT2:

I've been searching a bit more about this - I found out it's a technique called bit-banging. I've kinda reduced my particular problem to the chip enable/select phase of what I'm trying to achieve. It isn't very clear to me how the serial load and the read clock pins fit in the picture.

There must be a sequence in which they are brought high (or low) as to enable the clocking out to the QH pin via toggling the serial clock pin. This is fundamentally what I'm trying to understand.

EDIT3:

Following @shuckc's answer I need to clarify the following:

• The pin doesn't directly connect the shift-register and the PIC. There are level-shifters between them. Voltage-wise, the signals are correctly adapted.
• The fact that the shift-register design being used is 30 years old is out of my control. I'm working on a circuit built with components that have been stored for quite some time and were used to prototype a design concept. I have no other option, ATM.
• What I'm trying to understand is the sequence of signals I need to enter at the shift-register so I can output the latched bits serially. This aims to READ into the PIC from the SERIAL OUTPUT of the shift-register.

Right now what I'm trying to do is something in the line of:

enableShiftRegister() // OE pin in SR ->High; SLOAD pin in SR -> High
latchSignal(); // LATCH_PIN = SET; delayNs(2); LATCH_PIN = CLEAR - RCLK in SR
for(i=0; i<8; i++){
clockSR(); // SRCLK_PIN = SET; delayNs(2); SRCLK_PIN = CLEAR; - SRCLK in SR
sdiBus = SDI_BUS;
}


The delayNs(x) function delays the CPU for x nanoseconds. I also tried to explain which pin in the SR is being controlled by which PIC pin - remember: they are voltage adapted, so that is not a question.

• Why not generate the serial bit stream directly on a PIC pin? There's built in peripherals to get accurate timing over a wide range of baud rates. Apr 11 '14 at 14:13
• @shuckc because this is what I need to do and I don't have that option. The SDI_BUS line is common to several modules that are daisy-chained and each module has a bunch of shift-registers with photodiodes connected to their paralel load pins. I need to know how to operate the shift register so I can fetch the data in those pins sequentially.
– Joum
Apr 11 '14 at 14:22
• Ah OK, sounds like you are a lot closer than the initial question sounded! Apr 11 '14 at 18:06

If I understand your question correctly, it is important to understand that the device works in a couple separate stages.

1. The parallel inputs. These have latches that must be signaled to read the inputs and internally hold their state. Once latched, the signal on the input pins can change but the internal signals will be stable. (RCK)
2. The next step is where these internal signals are copied into the shift register. ($\overline{\small \text{SLOAD}}$)
3. The last step is shifting out the bits in the shift register (SCK)

If I understand the truth table and timing diagram in the datasheet correctly then the correct order of steps is the following:

1. Initialize the signals as follows RCK = low; $\overline{\small \text{SLOAD}}$ = high; $\overline{\small \text{OE}}$ = low; SCK = low;
2. Apply parallel signals to the inputs A~H
3. Clock the parallel signals into the latches by driving RCK high. RCK triggers on a rising edge. Drive RCK low, its inactive state.
4. Copy the contents of the input latches into the shift register by driving $\overline{\small \text{SLOAD}}$ low. $\overline{\small \text{SLOAD}}$ is active low. Drive $\overline{\small \text{SLOAD}}$ high again, its inactive state.
6. Apply a clock pulse on SCK to shift the data out on pin QH. SCK triggers on a rising edge. Drive it high, then low.
7. Repeat last 2 steps for as many inputs as you are interested in.
• Just to be perfectly clear with respect to step 4, $\overline{\small \text{SLOAD}}$ is NOT edge-triggered. The shift register contents are forced to match the contents of the input register whenever $\overline{\small \text{SLOAD}}$ is low. You must drive it high before you can shift anything. Furthermore, with respect to step 5, the first output (the one corresponding to input H) is available immediately on $Q_H$, before you apply a rising edge to SCK. Steps 5 and 6 should really be swapped. Apr 14 '14 at 1:07
• @DaveTweed Good catch with the edge trigger, not sure why I wrote that. Probably mixed up two signals. For Q<sub>H</sub> I misread the timing diagram. Corrected both. Apr 14 '14 at 4:52
• This is exactly the type of answer I was looking for, thank you both! Is there anything you can add in terms of timing? ie, how long should $\overline{\small \text{SLOAD}}$ be driven high? Should I introduce some delay between the steps? Something like a couple of nanoseconds, or so?
– Joum
Apr 14 '14 at 8:53
• @Joum Check under 'AC electrical characteristics' in the datasheet, most setup times are max in the order of 20ns for 5V. Your controller probably runs at couple MHz and it will probably be 'too slow' (<50MHz) to really be a problem. Apr 14 '14 at 11:51

Generally it would be easier to generate/receive the serial bit stream directly on a PIC pin, rather than use an external parallel-to-serial converter. Especially one that's a 30 years old design. The PIC has built in HSSI peripherals to get accurate timing over a wide range of baud rates if you need to maintain a tight bitrate UART/USB/I2C whatever.

Relating to your question - firstly consider the interface between the 3.3V PIC and the inputs on the 74HC589. Do you have any voltage buffers/drivers between the chips? Are the PIC outputs (3.3V) high enough at logic 1 levels to register cleanly as a 1 in the 74HC589? This is VIH 'Minimum HIGH Level Input Voltage' in the datasheet. To check this we need to know how you have connected the power rails of the 74HC589, what's its supply voltage?

You'll need to drive the parallel bit pattern on the "PARALLEL DATA PINS" at least 20ns before the strobe on R-CLOCK, (SETUP TIME) so you'll need a few instructions before you raise R-CLOCK. The hold time is min 5ns so you don't need to keep R-CLOCK high for long. What does your software code look like that performs the parallel load?

-- update --

You are trying to READ from this device? I'll need a circuit diagram or better description to understand.

• Thanks for trying to help! Please check my edits in the question.
– Joum
Apr 11 '14 at 16:40