I'm using a PISO shift-register, specifically the Fairchild Semiconductor 74HC589.
I got the jist of the workings of a generic shift-register via the very useful animated GIF in Wikipedia link above, although, there is a step that is elluding me:
- According to the datasheet, there is a Serial Load pin (13) and a Read Clock pin (12). Supose I just want to load whatever is in the input latches to the shift-register itself and then simply clock the bits out one by one to the serial output pin. What kind of signal/timing sequence am I looking for?
As I figure it out, the serial load pin should be activated to latch the input pins and then the read clock should transfer from the latches to the shift-register, right?
I need to know this because I'm controlling the SR via a PIC32MX and for now I need to know how I can SET
or CLEAR
the pins I have connected to the SR so I can then read serially in other PIC32 pin.
Any thoughts?
EDIT:
To help everyone understand my question (hopefully) a bit better, each pin on the shift-register is directly connected to a pin in the PIC32. For instance:
#define READ_CLK PORTFbits.RF0
#define READ_CLK_TRIS TRISFbits.TRISF0
#define SERIAL_LOAD PORTEbits.RE4
#define SERIAL_LOAD_TRIS TRISEbits.TRISE4
#define SR_CLK PORTEbits.RE3
#define SR_CLK_TRIS TRISEbits.TRISE3
#define SDI_BUS PORTEbits.RE2
#define SDI_BUS_TRIS TRISEbits.TRISE2
This way, by SET
ing or CLEAR
ing each signal, I can enable/disable the pins in the shift-register.
In the end, the idea would be to read in the PIC's SDI_BUS
pin whatever comes out of the shift-register's QH (pin 9) output.
EDIT2:
I've been searching a bit more about this - I found out it's a technique called bit-banging. I've kinda reduced my particular problem to the chip enable/select phase of what I'm trying to achieve. It isn't very clear to me how the serial load and the read clock pins fit in the picture.
There must be a sequence in which they are brought high (or low) as to enable the clocking out to the QH pin via toggling the serial clock pin. This is fundamentally what I'm trying to understand.
EDIT3:
Following @shuckc's answer I need to clarify the following:
- The pin doesn't directly connect the shift-register and the PIC. There are level-shifters between them. Voltage-wise, the signals are correctly adapted.
- The fact that the shift-register design being used is 30 years old is out of my control. I'm working on a circuit built with components that have been stored for quite some time and were used to prototype a design concept. I have no other option, ATM.
- What I'm trying to understand is the sequence of signals I need to enter at the shift-register so I can output the latched bits serially. This aims to READ into the PIC from the SERIAL OUTPUT of the shift-register.
Right now what I'm trying to do is something in the line of:
enableShiftRegister() // OE pin in SR ->High; SLOAD pin in SR -> High
latchSignal(); // LATCH_PIN = SET; delayNs(2); LATCH_PIN = CLEAR - RCLK in SR
loadSR(); // SLOAD_PIN = CLEAR; delayNs(2); SLOAD_PIN = SET;
for(i=0; i<8; i++){
clockSR(); // SRCLK_PIN = SET; delayNs(2); SRCLK_PIN = CLEAR; - SRCLK in SR
sdiBus = SDI_BUS;
}
The delayNs(x)
function delays the CPU for x
nanoseconds. I also tried to explain which pin in the SR is being controlled by which PIC pin - remember: they are voltage adapted, so that is not a question.
SDI_BUS
line is common to several modules that are daisy-chained and each module has a bunch of shift-registers with photodiodes connected to their paralel load pins. I need to know how to operate the shift register so I can fetch the data in those pins sequentially. \$\endgroup\$