I'm trying to use a Xilinx xc9536xl to decode a current modulated signal but am having an issue with the pull ups on the pin. From what I've gathered the CPLD has pull-ups on the order of 10s of k ohms and they cannot be turned off which I did not anticipate.

The problem is that my circuit uses 500k resistor to generate the desired voltage level which is no where near strong enough to pull the CPLD input back down.

I have a PMOS currently available on the design that I could use and I've attached a proposed modification (in red) that I tried to implement unsuccessfully. Basically I'm trying to translate the 6V pulses on the output of the opamp into clean, 3V pulses on the input of the CPLD. Does anyone have any other suggestions to solve this issue?

Edit: In order to solve the problem initially, I fed the output of the opamp directly to the CPLD, however this swings from 0-6V which while tolerable isn't ideal, and it is not a very clean pulse.

After implementing my suggested changes, the output of the opamp only swings goes as high as 2V on most pulses (3V on some) and I'm missing pulses on the CPLD input.

Edit #2: Modified the circuit to remove opamp feedback and now I'm getting nice clean 6V pulses on G1 (0~6V) and the inverse on G2 (0~3V). The issue is that without the feedback loop I'm seeing some weird behaviour at the end of the pulses I wasn't seeing before.

Further, if the feedback loop is not required as I've found, would it make more sense to connect D1 to 3V3, replace the 500k with a strong pull down and drive the CPLD off S1? Should I put a series resistor on G1?

enter image description here enter image description here

Edit #3: Modified the circuit to use NMOS to drive CPLD directly. Without the feedback circuit I was able to replace the weak pulldown with a strong one and eliminate the need for the PMOS or to invert CPLD input. The stray pulses at the end of the data still exist without the feedback circuit. Any idea what's causing it?

Edit #4: Stray pulses are still there after adding hysteresis, but the pulses are much cleaner. I think the driver is actually generating these pulses unnecessarily.

  • \$\begingroup\$ What are the part numbers of the opamp and the transistor pair? And what are the supply voltages on the opamp? One potential problem I see is that if the threshold voltage of the N-FET is too large, preventing its source from rising to 3.3V, the P-FET will never be completely cut off. \$\endgroup\$
    – Dave Tweed
    Mar 20, 2014 at 21:22
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    \$\begingroup\$ OK, since the gate of the P-FET isolates the opamp from the CPLD, then it's clear that it's the negative feedback that's killing your pulse heights. Try connecting the drain of the N-FET directly to +6V, instead of connecting it to the positive input of the opamp. \$\endgroup\$
    – Dave Tweed
    Mar 20, 2014 at 21:41
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    \$\begingroup\$ Regarding your third edit: This is why I suggested positive feedback; your longer pulses have a slow decay, and you're getting a burst of noise as it passes through the switching threshold. I would recommend reducing the 7K and 2M resistors to 700 ohms and 200K, respectively, and then adding a 10M resistor between the opamp output and the noninverting input. This will give you about 0.42 mV of hysteresis, which should clean up the output transistions considerably. \$\endgroup\$
    – Dave Tweed
    Mar 21, 2014 at 1:20

1 Answer 1


You're using the N-FET as a source follower, which is fine, but you've wired the P-FET up in such a way that it will invert the pulses — i.e., when the opamp is high, the CPLD input will be low, and vice-versa. Did you account for this in your CPLD design?

However, it isn't clear to me why you have the drain of the N-FET connected back to the noninverting input of the opamp, which creates a certain amount of negative feedback.

  • \$\begingroup\$ I realize that this will invert the signal- I haven't accounted for this in the CPLD yet but for now I'm just monitoring the input of the CPLD anyway. I didn't design the original circuit but I believe the feedback is necessary to keep the opamp from becoming unstable. \$\endgroup\$
    – spizzak
    Mar 20, 2014 at 20:55
  • \$\begingroup\$ I just wondered, since it looks like the opamp is otherwise just being used as a comparator, and normally you'd want some positive feedback in this configuration to create some hysteresis. But getting back to your question, in what way was your modified circuit "unsuccessful"? You never said. \$\endgroup\$
    – Dave Tweed
    Mar 20, 2014 at 21:14

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