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Here I attached the routed nets for this below verilog HDL program with DCM instantiate module. while I am implementing in XC3S50AN FPGA board using using ISE12.3 Design suite clk2x & locked outputs are not providing any output in SPARTAN FPGA development board (https://www.pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an) there is an output LED'S are assigned for clk0,locked,clk2x pins (p7,p8,p10 in datasheet) are output ,pins and (p57(clk),p18(rst)) are input pins.but, i got an output only at the clk0(p7) that is 2.5 Mhz same as clk50(intenaly generated clock from 50Mhz of input clock)

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module dcm_pllverilog(clk,rst,clk0,clk2x,locked);

input clk;
input rst;
output clk0;  
output clk2x;
output locked;

reg clk50=0;
wire clk0;
wire clk2x;
wire locked;

reg [7:0] count=0;

clkdcm_test instance_name (
    .CLKIN_IN(clk50), 
    .RST_IN(rst), 
    .CLK0_OUT(clk0), 
    .CLK2X_OUT(clk2x), 
    .LOCKED_OUT(locked)
    );

always @(posedge clk) //---2.5 Mhz signal from 50 MHZ crystal oscillator 
begin 
     count<=count+1;

  if(count<=9) 
     clk50<=1;
  if(count>=10)
     clk50<=0;
  if(count>=19)
     count<=0;
end
endmodule



//----------

# PlanAhead Generated physical constraints 

NET "clk" LOC = P57;
NET "clk0" LOC = P7;
TIMESPEC"Ts_clk" = PERIOD "clk" 20ns high 50%;
NET "clk2x" LOC = P8;
NET "locked" LOC = P10;
NET "rst" LOC = P18;

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Basically what it is saying is that there is a fast path (a direct connection) from certain pins into the DCM but for some reason this fast path can't be used. This could be for a number of reasons. If I'm reading the datasheet right, P53 isn't a clock capable pin so there won't be a fast path. You can also get problems if you've LOC'd the DCM to the wrong site in the UCF or you are using many DCMs such that the ideal site isn't available. Looking at your project though, it looks like this is the only thing in the design?

Where did you get the PAD53 constraint for the input clock?

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  • \$\begingroup\$ Thanks for your reply Mr hm2014.......... actualy i tried with PAD92 that also same error i got it .then i tried with pad 22 in that there is no error at all in all the implementation,configuration,mapping process but there wont have any output in the device hardware module . this is the device actualy i am using for design that web link is below pantechsolutions.net/project-kits/cpld-fpga-boards/spartan-3an (that device data sheet they have given PAD92 as clock input pin like . i assigned all dcm output to led pins in that device also reset for switch in that.but no response. \$\endgroup\$ – user39051 Mar 22 '14 at 4:03
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If you take a look at your routed design, you will see that the DCMs inside the SPartan 3A device are placed on the 4 side of the IC. There are 'dedicated' IOs or IOs with easy routing to the GCLKMux available close to those DCMs.

In this image you see the 2 DCM and the optimized IOs for those DCM on a SPARTAN 3A device:

enter image description here

I don't have access to the schematic and information about the board you are using but I am sure you will be able to find the right IoB for your clock if you look at the schematic of the board.

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  • \$\begingroup\$ But while i use this internal clock for DCM clkin input i am getting clk0 as perfect frequency of output same as internal clock but not in remaining o/p pins .i cahanged from previous coding like this and also schematic for that is attached in here............ \$\endgroup\$ – user39051 Mar 24 '14 at 9:45
  • \$\begingroup\$ When you are new with FPGAs and don't know the tricks of using those internal resources, you should definitely use the IP core generator to create a simple DCM for you, that way, you are 100% sure that the code works for your FPGA. \$\endgroup\$ – FarhadA Mar 25 '14 at 8:16

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