I work in MAGIC Integrated Circuit software at layout-level.

I got an 8bit dynamic register made of 1bit dynamic flipflops that write input on the positive edge of the signal:


(Note: I used Transmission gates as switches instead of just NMOS, for robustness. Inverters are normal CMOS inverters.)

So it basically has 8 of these flipflops, connected to the same CLK. However, when I just do simple CLK and notCLK propagation, my register works on BOTH the positive and negative edge of CLK, while it should work only on positive edge. My TA told me it's because of the Race Hazard, where at one point both CLK and notCLK are at high logical level, during transition. This was correct when I simulated, so I eliminated Race Hazard with this circuit:


And indeed, with this there was no overlapping of logical '1' for CLK and notCLK. Of course, there was overlapping of the '0's, but that's inevitable, and it shouldn't affect the circuit, right?

However, I still have the 8bit register writing input values at BOTH positive and negative CLK edges! Why does this still happen? It works correctly apart from this fact. Here's the signal diagram: diagram

As you can see, t2clk and t2nclk are my CLK and notCLK outputs of the race eliminator circuit, and it successfully eliminated '1' overlapping. However, it still writes values on negative edge of signals!

Heres my layout of the whole 8bit register, if its of any use:


If you need detailed layouts, I'll give, but I can guarantee they are faithful to my explanations! :) Help ASAP plz, deadline tomorrow!!! :)

EDIT: Could the addition of Transmission gates instead of NMOS' be the reason for malfunction?


1 Answer 1


Yes, if you replaced the NMOS transistors with full transmission gates, where the P and N transistor are on opposite clock phases, then you will have a race problem. Suppose your two clock phases are named PH1 and PH2. One of the transmission gates should be controlled with PH1 and ~PH1 and the other should be controlled by PH2 and ~PH2.

You cannot use PH2 as ~PH1 or use PH1 as ~PH2.

You must verify that the non-overlap condition still holds for the inverted phases as well as for the true phases. If you need to increase the non-overlap, add pairs of inverters in the feedback paths of the cross-coupled NOR gates.

  • 1
    \$\begingroup\$ Yes. A second clock generator circuit, this time using NAND gates, is required to generate ~PH1 and ~PH2. Also, you need to characterize the turn-off times of the transmission gates, and make sure the clock non-overlap time is larger by a comfortable margin. \$\endgroup\$
    – Dave Tweed
    Commented Mar 21, 2014 at 20:43
  • 1
    \$\begingroup\$ Joe has nailed it! however, you can generate all the signals you need with inverters on the Phi1 and Phi2 signals to get the (4) that you need. \$\endgroup\$ Commented Mar 21, 2014 at 20:57
  • \$\begingroup\$ Great answer! I considered adding either four signals to propagate through the circuit, or adding two inverters in each flipflop cell. I decided on the second option :) \$\endgroup\$
    – Vidak
    Commented Mar 24, 2014 at 16:29

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.