The best reference for my question would be this youtube video: https://www.youtube.com/watch?v=4VW017qPT6Y

I'm trying to do exactly what they did with the following resources:

  • Matlab 2013a with HDL Coder and various other packages
  • The DE2-115 FPGA board
  • A radio

So, first I am tasked with creating an AM transmitter, then FM, but for the context of this question I will concentrate on FM.

My main concern is how to transmit a signal of 88 MHz or greater if the internal clock of the DE2-115 is 50 MHz. So, how exactly did the group at Hasselt University transmit a signal greater than 88 MHz? Or, how would you?

The FM Modulator Passband Simulink block inputs and outputs double as the data type, so, I think I need to write my own function to replace the FM Modulator Passband block. But, can I?

Thank you for any and all responses! I'll answer any questions as quickly as possible.


You'll probably have to use HDL coder to create a sub-block with all your detailed processing in, and use the Altera tools to create you a PLL to multiply up your clock. Then build a top-level VHDL or Verilog file with the pins on it. Inside that you can instantiate your PLL and processing logic and wire them together.

It's very rare you can use a tool like HDL coder to build an entire FPGA system, you usually have to use it to create a sub-block.

  • \$\begingroup\$ That's what I was afraid to hear. This is turning out to be quite a "fun" senior design project. Thank you for your answer! \$\endgroup\$
    – Everlight
    Mar 25 '14 at 16:56

You use one of the on-chip PLLs (there are four of them in your device) to multiply the 50 MHz input clock to something higher, such as 200 MHz. That becomes the sample rate you use for the VGA output.

  • \$\begingroup\$ Thank you for your response! I haven't heard of or used PLLs before. Do you have any/recommend any example source code I could use? (Using HDL Coder) \$\endgroup\$
    – Everlight
    Mar 24 '14 at 22:19
  • \$\begingroup\$ Sorry, no. I do all of my FPGA coding directly in VHDL and Verilog. Perhaps someone else can help with that. \$\endgroup\$
    – Dave Tweed
    Mar 25 '14 at 4:57

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