I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there I encountered the phenomenon called a flip flop.
Schematics are like so:
Now I can read this diagram and conclude things based on the outcomes of each nor-gate. What I have a hard time wrapping my head around is the following. Say S=1 and R=0. Any NOR operations with any of the two inputs at 1 (or a high current I presume) ends with a 0 (low) output. In this case I can quietly forget that the second INPUT of the S-gate is the result of an operation that requires the OUTPUT of the same S-gate. There is a 1, I can pretend it doesn't matter where the other input comes from.
This makes Q a 1 since the output of the S-gate is 0 and the R-input is 0 as well. The problem starts when S-input is 0 and R-input is 0. This means "maintain state" or keep outputting a 1 at Q and a 0 at /Q (Not Q). In this case what wins? I simply can't understand how R can be based on output-S while S is based on output-R. At first I thought maybe R is always "first" and the lack of an output-S just means a 0-signal, but I don't know if this is really how it works and if S being 0 by default works in all cases.
Can anyone explain me the concepts that make this work in layman terms?