# Cross-coupled logic gates and timing

I had a hard time getting a right title for this question since I'm a software guy trying to get the basics of my hardware down. Since all computers basically start with logic gates and go from there I encountered the phenomenon called a flip flop.

Schematics are like so:

Now I can read this diagram and conclude things based on the outcomes of each nor-gate. What I have a hard time wrapping my head around is the following. Say S=1 and R=0. Any NOR operations with any of the two inputs at 1 (or a high current I presume) ends with a 0 (low) output. In this case I can quietly forget that the second INPUT of the S-gate is the result of an operation that requires the OUTPUT of the same S-gate. There is a 1, I can pretend it doesn't matter where the other input comes from.

This makes Q a 1 since the output of the S-gate is 0 and the R-input is 0 as well. The problem starts when S-input is 0 and R-input is 0. This means "maintain state" or keep outputting a 1 at Q and a 0 at /Q (Not Q). In this case what wins? I simply can't understand how R can be based on output-S while S is based on output-R. At first I thought maybe R is always "first" and the lack of an output-S just means a 0-signal, but I don't know if this is really how it works and if S being 0 by default works in all cases.

Can anyone explain me the concepts that make this work in layman terms?

It simply relies on the phenomenon called propagation delay. Consider the following circuit. When simulated, you'd find that it doesn't stabilize in either low or high state. It simply oscillates. If you were to probe such circuit in reality with a scope, you'd find that it's output has a somewhat fixed frequency - derived from the system's propagation delay.

simulate this circuit – Schematic created using CircuitLab

Getting a combinational circuit (like a gate) and feeding it with it's output often makes it sequential, that is history dependant, so to speak. What you have encountered is just a real world application of this very phenomenon - memory in this case.

It's noble from you to investigate these things from the inside, but in practice we often look away from the internals and behaviorally describe a flip flop based on what it does as a black box.

• Investigating from the inside is the whole point :D Does this mean that the flip flop is sort of confused for an amount of time (nanoseconds?) before it is in correct output state? Mar 26, 2014 at 10:36
• I guess you can say it like that :) Mar 26, 2014 at 10:37

Assume an initial condition S = 0, R = 0, Q = 0, Q_bar = 1.

(1) SR = 00

Now consider NOR1(top), inputs of this gate is R = 0, Q_bar = 1 this gives output Q = 0.

at NOR2, inputs are S = 0, Q = 0 this gives output Q_bar = 1.

(2) SR = 00 to 01 change occurs at R (0 to 1)

at NOR1, inputs are R = 1, Q_bar = 1 this gives output Q = 0.

at NOR2, inputs are S = 0, Q = 0 this gives output Q_bar = 1.

(3) SR = 00 to 10 change occurs at S (0 to 1)

at NOR2, inputs are S = 1, Q = 0 this gives output Q_bar = 0.

at NOR1, inputs are R = 0, Q_bar = 0 this gives output Q = 1.

(4) SR = 11 state will drive the flip flop into indefinite state

I tried to make it simple. Let me know if you need more clarification.

• Thanks for taking the time to answer. I gave correct answer to the other answer since it mentioned the terms I could use to investigate further, but thanks a ton! Mar 26, 2014 at 10:38
• Even I gave plus one for Dzarda's answer. He explained the concept in really cool way. :D Mar 26, 2014 at 11:30