In the datasheet (http://www.ti.com/lit/gpn/pcm1807) of the Texas Instruments PCM1807 in section ABSOLUTE MAXIMUM RATINGS (page 2) it says

Analog Input Voltage \$V_{IN}L,V_{IN}R,V_{REF}\$: \$-0.3V \text{ to } (V_{CC} + 0.3V\$)

Ok, that means it's a standard ADC for which an AC signal must be shifted before it's fed to the input pins. Oh, and there's a convinient \$V_{REF}\$ for the DC offset (aka center voltage) as well.

But the schematic in section TYPICAL CIRCUIT CONNECTION DIAGRAM (page 25) both \$V_{IN}L\ \text{ and } V_{IN}R\$ are connected using a capacitor, which removes the DC offset and makes it an AC signal again, obviously conflicting with the absolute maximum ratings (and the overall logic of level shifting the input voltage to the \$0-V_{CC}\$ range).

What did I overlook?

  • \$\begingroup\$ Yeah, looks weird to me as well... \$\endgroup\$ – Dzarda Mar 28 '14 at 14:25
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    \$\begingroup\$ It's definitely not clear but I believe you can assume the inputs are biased internally at 0.5 x Vcc - the diagram on page 25 indicates external coupling capacitors are needed with the positive side being at the chip. \$\endgroup\$ – Andy aka Mar 28 '14 at 14:48
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    \$\begingroup\$ Yes, with an input impedance of just 60K, you can assume that this is the Thevenin equivalent resistance of the internal bias network. The purpose of the Vref pin is so that an external bypass capacitor can be attached to that node, improving the PSRR. \$\endgroup\$ – Dave Tweed Mar 28 '14 at 15:05
  • \$\begingroup\$ So the ABSOLUTE MAXIMUM RATINGS are probably wrong? In the datasheet for the PCM1851A, it's also stated that the caps are needed to remove DC, but the analog input voltages are specified as \$-3 \text{ to } (V_{CC} + 3)\$ \$\endgroup\$ – apriori Mar 28 '14 at 22:27

Here's an application sheet for the PCM1807. Note the circuitry contained inside: -

enter image description here

Clearly, the analogue circuits only make an AC connection to the device's inputs. From this I assume that the basic input of the PCM1807 is biased at a suitable voltage and this bias voltage should not be disturbed without incurring possible loss of performance.

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