1
\$\begingroup\$

I have tried to come up with a schematic of using AD9838. I used the eval. board schematic and modified it to my needs. The eval. board schematic can be found on page 9 here:

AD9838 eval. board schematic

And my versions looks like this:

enter image description here

I have some concrete questions:

  1. The capacitor marked with red is not recommended in the data sheet and I don't know if it has any big effect except noise reduction. Should I keep it or not?

  2. The capacitor marked with green, I can not mentioned in the data sheet and I want to know what it does and if I have to include it.

  3. The two capacitors marked with blue is also not mentioned and I wonder how they effect the signal.

  4. The capacitors marked with yellow I assume are the bypass/decoupling caps?

  5. This circuit can be used with a 16 MHz crystal oscillator. I only have the HC-49 crystal and the recommended one is a Epson SMD with 3 ports. Can I connect the HC-49 directly to the MCLK pin or do I need to add additional components (resistor, capacitors?). This should be in the area marked pink. What do you recommend?

  6. Any other corrections/improvements are appreciated!

Here is the data sheet of the AD9838

\$\endgroup\$
2
\$\begingroup\$

1: the capacitor circled in red is optional, that is why there is a jumper link there. According to page 7 in the pin description tables:

"The regulator requires a decoupling capacitor of 100 nF typical, which is connected from CAP/2.5V to DGND"

Therefore, just use the 100nf cap.

2: AS before, in the pin function table page 8 the COMP pin needs that cap because: "DAC Bias Pin. This pin is used for decoupling the DAC bias voltage"

3: The two blue capacitors on the IOUT pins are usually not loaded, as the schematic suggests "DNI" or "DNL" means do not load (its not normal to have it there). If you had a mostly DC output and there is high frequency noise issues on the output, i guess you could put those there to give a cleaner output.

4: The yellow power supply AVDD and DVDD are indeed power supply decoupling capacitors. You should place these on PCB close to the IC pins associated with those supply rails. C6 and C7 should be placed as close as possible to Pin 2 of the IC. C8 and C9 should be placed as close as possible to Pin 1 of the IC.

5: In the schematic of the datasheet at the end, the one that you have referenced and blocked out some parts - there is a clock generator IC, or an optional CLK input pin. This means the chip doesnt actually have a proper crystal driver inside. You cannot therefore give it a crystal with load caps (usually in the 18-33pF range) because it cannot drive the signal itself. You must supply it with an externally generated clock signal. Description for Pin 5 (MCLK) is as follows:

"Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock."

So you must give it a proper clock, not a crystal (analog style clock i supposed you could consider a crystal)

6: good luck mate! Following the evaluation board schematic is a safe bet. Any other questions, don't hesitate to ask.

\$\endgroup\$
  • \$\begingroup\$ Maybe I should drive the AD9838 with a PWM, or just toggle GPIO with a timer? I am worried about the accuracy. Will this do? \$\endgroup\$ – iQt Mar 30 '14 at 10:31
  • \$\begingroup\$ PWM could work, but very very low. the output DDS signals are just a divisor of the MCLK signal, probably used as a reference signal for a N-divisor clock generator for output signal generation. If you used a 1MHz PWM output or even something slower if it's okay for the output, then it WILL work. \$\endgroup\$ – KyranF Mar 30 '14 at 10:49
  • \$\begingroup\$ @Phataas actually the datasheet for MCLK says minimum timing is 200ns period, so you MUST have >= 5MHz on the master clock input. \$\endgroup\$ – KyranF Mar 30 '14 at 10:52
  • \$\begingroup\$ Thank you for the help. I will try this tomorrow and give feedback =) \$\endgroup\$ – iQt Mar 30 '14 at 19:12
  • \$\begingroup\$ @KyranF Minimum period == maximum frequency. 5MHz is the maximum speed of grade A devices. \$\endgroup\$ – Nick Johnson Dec 8 '14 at 17:05

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.