I'm trying to climb the Cadence learning curve, coming from an Eagle background.
My board is four-layer, with a ground plane underneath the top layer. I have a surface mount IC that has an exposed pad, which should be soldered to ground. I want to avoid putting vias in this pad. Since two edges are free of pins, I am trying to pour a copper region larger then the opening in the solder mask, and then I'll put the vias there, connecting it to the ground plane.
Here is the part:
In Eagle, I would pour the polygon and assign it the same net name as the exposed pad. The two areas would merge nicely.
I have done this in Cadence, using a dynamic copper fill, on the top layer, and assigning the same net name ("GND_SIGNAL"). The two areas do not connect, and I get a trace between the two "floating" areas, connecting them to the exposed pad:
I suspect that this may be thermal relief between the pad and the pour. Is there a method to force Cadence to NOT use thermal reliefs, on just this one pad? I've looked over the docs, and asked google, but I'm not finding an answer.
Of course, it may be something else completely. Does anybody know how to do this?