Connecting copper pours in Cadence (OrCAD) PCB Designer

Question

I'm trying to climb the Cadence learning curve, coming from an Eagle background.

My board is four-layer, with a ground plane underneath the top layer. I have a surface mount IC that has an exposed pad, which should be soldered to ground. I want to avoid putting vias in this pad. Since two edges are free of pins, I am trying to pour a copper region larger then the opening in the solder mask, and then I'll put the vias there, connecting it to the ground plane.

Here is the part:

In Eagle, I would pour the polygon and assign it the same net name as the exposed pad. The two areas would merge nicely.

I have done this in Cadence, using a dynamic copper fill, on the top layer, and assigning the same net name ("GND_SIGNAL"). The two areas do not connect, and I get a trace between the two "floating" areas, connecting them to the exposed pad:

I suspect that this may be thermal relief between the pad and the pour. Is there a method to force Cadence to NOT use thermal reliefs, on just this one pad? I've looked over the docs, and asked google, but I'm not finding an answer.

Of course, it may be something else completely. Does anybody know how to do this?

Answer 1

I finally called Cadence support, and they were very helpful! Maybe there's a good reason to pay for their Maintenance Contract :) This answer is for PCB Designer 16.6. I don't know if it will be the same for earlier versions...

There are two methods to suppress thermals: the Global method, and the Instance method. The instance method only affects a single (dynamic copper) shape.

Since thermal reliefs are generally helpful, I don't want to turn them off globally. The Instance method, on the other hand, is just what I was looking for.

To set up the parameters for a specific instance, select the shape, then right-click. Choose "Parameters..."

Or, if you prefer a global change, click on Shape > Global Dynamic Params. Either way, it brings up the same window. (you'd better remember which path you took to get there...)

Go to the "Thermal relief connects" tab. Under Smd Pins, choose "Full Contact". Perfect!

Take care everyone. Happy Engineering :)

Answer 2

Is there a method to force Cadence to NOT use thermal reliefs, on just this one pad [or just some selected pads] ?

I had the same question for a while, and I couldn't find a proper way to do this: neither for old OrCAD 10.5, nor for newer versions.

My workaround is to put a copper area (in addition to the copper pour) over the thermal pads. Unlike a copper pour, a copper area doesn't isolate tracks and doesn't have thermal relief. The copper area is connected to the same net as the thermal pad and copper pour. Copper area is larger than the thermal relief.

P.S. Hopefully that there is a better way of doing this. I'll keep an eye on this thread.

Answer 3

An old thread, I know, but in case anyone comes across it - the correct answer is DON"T DO THAT! Don't bypass the thermal reliefs. They are there for a reason. When your board goes through the tunnel the part will not stay where you want it to if there is a giant mass of ground plane attached to the thermal pad. The copper will suck out all the heat that is supposed to be melting the solder and making a good joint. The part may float up or twist or just not get soldered at all. A very bad practice. If you are at the very limits of your thermal design (a bad place to be, poor design) and need every ounce of copper to keep your chip from burning up you can: 1. Increase the size of the thermal spokes by changing them in the Constraint Manager. 2. Put in an array of vias to a ground plane in another layer or on the back side or even to a large copper area on an inner layer. If the vias have the minimum hole size or are tented on the bottom side it will prevent the solder from escaping through them. They don't have to be filled. You should do this anyway.

I know all the part manufacturers' example boards and sample designs show massive copper planes right under the pads with no reliefs, but they only do that because it makes the chip look better in the thermal image test. If you want decent yields in production, use a higher power chip, don't run it at the limits and use thermal reliefs. The Contract Manufacturer has spoken.