My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal that changes with the fast clock. At present all I've done is loopback the signals from the audio board into the FPGA back to the audio board. I can do this same loopback bypassing the FPGA and the signal integrity is fine. The problem is when I route through the FPGA. At the output pins at every fast clock transition there is significant noise on the slow clock, so much so that it sometimes changes logic level. How do I isolate these from each other effectively? Thes pins on the daughterboard are currently right next to each other. Would moving the pin assignments make a difference or would it not matter because the wires will still be next to each other?

Thanks for any advice!

  • \$\begingroup\$ How about a link to the audio card for the non-psychic amongst us? \$\endgroup\$
    – Andy aka
    Commented Apr 1, 2014 at 7:21
  • 1
    \$\begingroup\$ Use separate cables with grounded shields. \$\endgroup\$ Commented Apr 1, 2014 at 8:14
  • \$\begingroup\$ I don't know why it matters but this is the audio board: maximintegrated.com/datasheet/index.mvp/id/7184 \$\endgroup\$
    – ballaw
    Commented Apr 2, 2014 at 21:58

2 Answers 2


Some things I'd try:

  • Use the slowest drive you can get away with. At these clock rates, you should be able to use very slow drivers. You don't mention a specific FPGA type, but if it were Xilinx, I'd be using the "quiet" drivers, or "slow" if not available, and a 4mA drive current. See how it looks on the scope, increase the drive current if necessary.
  • Twist a ground wire with each of your signals, or at least with the clock signals. Or if using ribbon cable, put a ground on either side of both the clocks. Keep the clocks well away from each other. In the extreme, use coax for the clocks (but be careful to use a very short connection to ground for the shield, otherwise you stand a good chance of not gaining anything)

You have to think about how the current is flowing - both "out" and "back" - any time the current of one signal mixes with another (say using a single ground return wire), you will have potential for problems.

Another suggestion - in order to understand what's going on so you can predict these problems next time, read (and inwardly digest :) a book on signal integrity

  • \$\begingroup\$ With Howies book referenced make sure you get the extensive errata list as well. Or get one of the newer books from Eric Bogatin or Lee Ritchey (Disclaimer: I organize training with Lee Ritchey + I have his first book for free download on my website. Despite all this, I really objectively think the books I mentioned are better bets today if you read only one book on the subject.) \$\endgroup\$ Commented Apr 2, 2014 at 6:48
  • \$\begingroup\$ @RolfOstergaard: Yes, Eric's book might be a better starting point these days. Lee's I haven't read, so can't comment. \$\endgroup\$ Commented Apr 2, 2014 at 8:38
  • \$\begingroup\$ @RolfOstergaard - I've updated the "books" link to be more generic. \$\endgroup\$ Commented Apr 3, 2014 at 15:45

A picture here would be really good to understand your setup.

First: Crosstalk is inductively and/or capacitively coupled. If your wires are just individual widely spaced wires in the air, you most likely do not have much of either.

At that length you will have reflections if you don't manage that correctly. Reflections can easily cause double-clocking. With individual wires in the air, the impedance is quite unpredictable. You need to bring the wires close to a reference (ground) to have a predictable impedance. One good way to do this is using a ribbon cable with a Gnd-Signal-Gnd-Signal-Gnd pattern.

Once you have done that, you can terminate the signals using a series termination resistor at the driver end of each signal - or you can program your FPGA (if that is the driver of all signals?) to have sufficiently high output impedance to match the impedance of the ribbon cable (in FPGA terms that is called lower output drive strength).

The G-S-G-S-G pattern will also take care of another (even worse) problem you are likely seeing. The inductance of the (single?) return wire creates a voltage drop (L * di/dt) every time the signals change. This can look like crosstalk. By having about as many return wires as you have signal wires, this is normally not an issue.

Just think about it. Say you switch 4 signals in 400ps and you have close to 2uH in a single return wire with a current of 16mA per output that could create a voltage drop of 4 * 2uH * 16mA/400ps (way more than your supply voltage). In reality that is a gross overestimation, but you are sure to see the impact on your signals pretty badly.

Let me know if this solved your problem?

  • \$\begingroup\$ Thank you so much for your help but I think it might actually a grounding problem now. I think those spikes were just an oscope thing since removing one of the probes made the noise mostly go away on on of the signals. I remade the wires and put them into stable connectors and the noise partially went away. Now there's noise unless I fiddle around with the grounding wire. I would like to follow Martin's advice and twist a ground wire around each clock but the headers these signals come out of limit me. There are any ground I can terminate on on the audio eval board. \$\endgroup\$
    – ballaw
    Commented Apr 2, 2014 at 21:57

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