My setup is as follows. I have 6 foot long 22-gauge wires connecting pin headers of an audio codec eval board and an FPGA daughterboard. I am sending an 8KHz and 128KHz clock signals and a data signal that changes with the fast clock. At present all I've done is loopback the signals from the audio board into the FPGA back to the audio board. I can do this same loopback bypassing the FPGA and the signal integrity is fine. The problem is when I route through the FPGA. At the output pins at every fast clock transition there is significant noise on the slow clock, so much so that it sometimes changes logic level. How do I isolate these from each other effectively? Thes pins on the daughterboard are currently right next to each other. Would moving the pin assignments make a difference or would it not matter because the wires will still be next to each other?
Thanks for any advice!