The time required for a gate to switch is dependent upon the amount of capacitive load it must drive, the size of the transistors, and the number of transistors in series. An inverter consists of one NFET (N-channel Field Effect Transistor) and one PFET (P-channel FET); a three-input NAND gate has three PFETs in parallel and three NFETs in series. In order for a 3-input NAND gate to switch an output low as quickly as could an inverter, each of the three NFETs would have to be three times as big as would be the single NFET of an inverter.
For a small chip such as this one, the only transistors which have to drive any significant load are those connected to output pins. Using four outputs driven by inverters, it will be necessary to have four big PFETs and four big NFETs, plus a bunch of little ones. If one assigns the NFETs an area of "1", the PFETs would probably have an area of about 1.5 (P-channel material doesn't work quite as well as N-channel), for a total area of about 10. If the outputs were driven directly by NAND gates, it would be necessary to use twelve big PFETs (total area 18) and twelve huge NFETs (total area 36, for a total area of about 54. Adding 20 little NFETs and 20 little PFETs [12 each for the NAND, and 8 each for inverters] the circuit will reduce the area consumed by big transistors by 44 units-more than 80%!
Although there are some occasions when an output pin will be driven directly by a "logic gate" other than an inverter, driving outputs in such a fashion increases greatly the area required for output transistors; it's generally only worthwhile in cases where e.g. a device has two power-supply inputs and it must be able to drive its output low even when only one supply is working.