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My basic understanding of using a shift register to convert serial to parallel data is this:

  1. On every clock pulse, the state of the serial data pin is read
  2. As data is read, it gets shifted in to the registers
  3. When the latch pin pulses the values in the register are sent to the parallel output pins

Here is a timing diagram for the 74HC595.

enter image description here

SH_CP is the clock, and DS is the serial data pin. To begin with DS is low, and then it goes high and then the latch starts pulsing... Then I don't really get it. As it stands I don't understand what this diagram explains or how it is useful to me.

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There is quite a lot going on in this diagram.

  • The up arrows on the clock are telling you that things are sampled on the positive edge of the clock

  • DS is the data going in, you can see that it is sampled on the positive edge of SH_CP. (sample and hold clock, positive edge)

  • It the comes out of Q0 on the first positive edge of ST_CP (shift register clock, positive again)

  • The pulse then appears at Q1 on the next clock and so on

So the diagram is showing that it is shifting the serial input from one output to the next to the next.

It also shows that bringing MR low resets the internal memory, but outputs Q0-Q7 remain at their state until the next state. The last output, Q7*, seems to change on the negative edge and be reset immediately.

Last of all, if OE(bar) goes high the the outputs all transition to high impedance.

Does that help?

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  • \$\begingroup\$ Very helpful answer! I have one more question, what does sample and hold mean? And why need to hold after sample? (BTW, I am new to digital circuit. Excuse me if this is naive question.) \$\endgroup\$ – smwikipedia Oct 6 '16 at 9:00
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    \$\begingroup\$ Sample-and-hold is the process of taking the input value and storing it so that the chip can act on it. The data is sampled as the clock rises and is then held at that value until the next rising clock. This is how synchronous logic works - you can google for the difference between synchronous and asynchronous logic. Synchronous logic like this is the more common of the two and by having things happen all at the same time and then not in-between it makes the system easier to understand and analyse \$\endgroup\$ – Will Oct 7 '16 at 14:41

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