I am using the CD4046BC for the first time, and do not understand something that is happening. I am using the type I phase comparator, which is just a simple XOR logic gate. When I have the input as a 50% duty cycle square wave with a frequency close to the carrier frequency that I've set for the chip, I do get a lock, but it is very unstable. As in, my lock range should be from 60 kHz to 140 kHz, and yet I'll establish a lock at 100 kHz and adjusting this by hundreds of hertz will bump me out of lock. I took a look at what was going on with the phase comparator, and the result does not make sense to me. I took the following picture when the signal was tentatively locked: the top is the input, the middle is the output of the VCO, and the bottom is supposedly the phase comparator...

enter image description here

Adjusting the frequency of the input to view the changes in the VCO output, it was clear to me that the phase comparator output was exactly the output of the VCO, albeit a different amplitude. Why in the world would this be the case? Has this ever happened to someone before? If not, do you know what is going on? I am very confused as to why this would happen. Many thanks in advance for any assistance.

Edit: Here is a schematic of the circuit that I am testing. It is simply a block diagram of the inside of the CD4046BC with my specific component values in red. Note that INHIBIT is grounded to enable the VCO, and the reference voltage Vss is also at ground. Here is a brief explanation of the components: R1, R2, and C1 establish the frequency range and its offset to be (100 +/- 40) kHz, R3 and C2 are components of a low-pass filter with a 5 kHz cutoff, and Rs is specified to be 10 k in the datasheet if this pin is used (can ignore it for this post).

enter image description here

In reference to my oscilloscope image, the top wave is at pin 14 (from a function generator), the middle is at pin 4, and the bottom is at pin 2.

  • \$\begingroup\$ A circuit would help. \$\endgroup\$ – Andy aka Apr 4 '14 at 8:01
  • \$\begingroup\$ Paraphrasing a bit what Andy said - this question can't get any answer before you show us the connections of the chip. \$\endgroup\$ – Vasiliy Apr 4 '14 at 10:51
  • \$\begingroup\$ @Andyaka Sorry about that. I edited my original post to include a circuit diagram and brief explanation, but can go into more depth if necessary. With that shown, it will now probably be clear why I am confused by how this chip is behaving. If pin three is the output of an XOR gate then my image makes no sense. Any thoughts? \$\endgroup\$ – dsm Apr 4 '14 at 15:15
  • \$\begingroup\$ @Vasiliy See my above comment to Andy, sorry about that. \$\endgroup\$ – dsm Apr 4 '14 at 15:15
  • \$\begingroup\$ @Andyaka I meant to say "If pin two is the output of and XOR gate..." My bottom signal is at pin two, not three. \$\endgroup\$ – dsm Apr 4 '14 at 15:22

Your reference oscillator p-p voltage is a 5V logic level: -

enter image description here

The chip is a standard 4000 series CMOS part that has voltage levels of: -

enter image description here

You're running at 10V and the guaranteed minimum high voltage level on a 10V supply is 7.5 volts. Do you see where this might be your problem?

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  • \$\begingroup\$ Thanks for the response Andy, I think I understand. The datasheet is saying that accurate operation is only guaranteed when the p-p input voltage is greater than 7.0 volts, and I was only supplying 5. Yes? However, why would the "Typ" be lower than the min? It seems like the datasheet is contradicting itself, but this is probably a just a flaw in my understanding. Equivalently, why would the "Typ" be greater than the max for the low-level input voltage? I really appreciate your help. \$\endgroup\$ – dsm Apr 4 '14 at 17:30
  • 2
    \$\begingroup\$ Welcome to the beautiful world of data sheets. \$\endgroup\$ – Andy aka Apr 4 '14 at 17:39
  • \$\begingroup\$ Typically 5 5 could/should work but 7.0 is the guarantee. For low levels everything is inverted so typically it might register a low at say 1volt but the guarantee might be 0.5. Ain't got data sheet in front of me so those last figures are half guesses. \$\endgroup\$ – Andy aka Apr 4 '14 at 17:48
  • \$\begingroup\$ Perfect, thanks! Surprisingly for the low it reads 3.0V for the max and a typical of 4.5V, so I can now easily see why this would behave badly for a 5V input. I'll be testing it a bit later today (hopefully) and will be updating this thread. \$\endgroup\$ – dsm Apr 4 '14 at 19:09

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