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I got an adder cell, which in IC mirror layout is this:

cell

EDIT: Transistor-level, standard adder circuit:

transistor-layout

Which I actually made in IC like this:

layout

It's not working as it should! I labelled it same as in the first figure, so the labels themselves are ok, but the signals are like this:

diagram

As you can see, the sum signal S is working as it should, but the carry output is buggy. Not only that, the COUT and notCOUT are not opposite, so sth is definitely wrong. I throuroughly examined the circuit, but can't find where I made a mistake.

Can anyone spot the error? THANKS!!

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  • \$\begingroup\$ Can you give us a transistor-level schematic of the circuit, a schematic that is known to function properly in SPICE simulations? \$\endgroup\$ – Joe Hass Apr 4 '14 at 14:56
  • \$\begingroup\$ @JoeHass added! :) \$\endgroup\$ – Vidak Apr 4 '14 at 14:59
  • \$\begingroup\$ Now can you label all of the internal nodes on the schematic, the stick diagram, and your layout? Also, please make the labels on the layout more readable. \$\endgroup\$ – Joe Hass Apr 4 '14 at 15:11
  • \$\begingroup\$ @JoeHass made labels more visible, will add internal nodes asap. Moreover, please note that the signal "cout" is behaving properly, apart from just being inverted from the expected value. Why do you think this is the case? \$\endgroup\$ – Vidak Apr 4 '14 at 16:12
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    \$\begingroup\$ If I understand the labeled layout correctly, you have NCout not driving anything. Yet in the schematic, you should have NCout driving an inverter to get Cout. You said this is a standard adder schematic, but what we really need is your adder schematic which doesn't match the standard adder schematic. \$\endgroup\$ – horta Apr 4 '14 at 17:59
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Ok, the whole problem was due to mislabelled nodes, here's the correctly labelled layout:

adderlayout

The circuit works as supposed, I just added the missing inverter at the end for acquiring the C_OUT signal :)

Thanks for help & insight @JoeHass and @horta

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If your schematic is what you're actually using, there's no way this will work with A getting applied to the two NMOS's in the second main column. The top A-input transistor should be a PMOS. The case of where Cin=1, A=1 and B=0 would create a short from the second main column down to ground through the second half of the first column.

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  • \$\begingroup\$ I'm sorry, I don't understand what you're saying :) What's the A-input transistor? \$\endgroup\$ – Vidak Apr 4 '14 at 15:58
  • \$\begingroup\$ You have two NMOS transistors vertically aligned to eachother in the 2nd main column that both have "A" as input. One of those needs to be a PMOS. The two "A" input transistors have a single "B" input transistor above and below that pair. \$\endgroup\$ – horta Apr 4 '14 at 16:03
  • \$\begingroup\$ I think that's just a typo in the schematic. I don't think the actual layout has that error. \$\endgroup\$ – Dave Tweed Apr 4 '14 at 16:20
  • \$\begingroup\$ You're probably right Dave. \$\endgroup\$ – horta Apr 4 '14 at 17:55
  • \$\begingroup\$ ooooh, yeah ofc it's a typo :D sorry! :) \$\endgroup\$ – Vidak Apr 5 '14 at 10:07

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