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I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of starting execution of the Extender , is dependent on the control logic , can anyone explain this misunderstanding ? the architecture of CPU MIPS

The timing diagram

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The timing of the "Second ALU Input" depends on three things:

  • the delay through the sign extender to the "1" input of the mux
  • the delay through the control logic to the select input of the mux
  • the worst-case propagation delay through the mux from either the "1" or select inputs

Yes, the labeling on the timing diagram is a bit unclear, but this is all they're saying. Either the path through the control logic or the path through the sign extender will be the long path that determines the final settling time for the second ALU input.

In static timing analysis, you need to take the worst case combination, and they seem to be implying that the worst case is the path through the control logic.

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  • \$\begingroup\$ so , the delay of the "Second ALU Input" , is not from extender neither MUX , it's just the delay of the path of Control to MUX ? \$\endgroup\$ – hbak Apr 6 '14 at 15:33

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